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SECTION 15
PROCESSOR MODULE (A9)
15-1
General. Primary control and data manipulation requirements of the system are performed by the
microprocessor on the Processor Module. Input and output information is carried along the processor's
address, data, and control buses, or displayed on the CRT through the character generator circuits on the
Processor Module. A block diagram of the Processor Module is shown in figure 15-1 with its schematic shown
in figure 15-2.
15-2. Processor.
A Motorola MC6802 microprocessor is the central part of the processor. The
microprocessor then accesses and controls the rest of the processor via three signal buses. The sixteen bit
address bus {AO-A15) determines which device on the bus the microprocessor will access. Data that will be
read from or written to the accessed device is contained on the seven bit data bus (DO-D?). Synchronization of
the data transfer and several specialized processor functions are provided by the control bus {HALT, NMI,
RESET, IRQ, VMA, E, and R/W).
15-3. The series of commands that direct the microprocessor's actions (software) is contained in the 16 K x 8
ROM (Read Only Memory). A standard unit has 12K x 8 ROM for the main program. With the IEEE option an
additional 4K x 8 ROM is added to provide the extra program required.
15-4. Temporary storage of microprocessor data is provided by 1Kx8 RAM {Random Access Memory). RAM
may be written into or read from by the microprocessor, and is used to store data generated by one part of the
program for use in another part of the program. Half of the RAM is reserved for storage of the data to be
displayed on the CRT.
15-5.
A Peripheral Interface Adapter (PIA) on the microprocessor bus provides input and output latches for
the front panel keyboard input {KYBD COL 0-3 and KYBD ROW 0-4), the IEEE option detector input (IEEE OPT
DET), the AF BUS EN1 signal line, and the nonvolatile memory (NVM). Data that is to be held during power off
is stored by the microprocessor in the NVM. Then when power is turned on the microprocessor reads the
contents of the NVM to obtain its start up mode, the RF and tone memory presets, and the rest of the preset
data. If the operator changes a preset, the microprocessor changes the data in the NVM so that the new preset
will be remembered. The NVM has a 42 x 8 or fourty two eight bit words capability.
15-6. Character Generator. The Character Generator sequentially accesses that half of RAM where
character information is stored and causes the respective characters to be displayed on the screen. Since both
the character generator and the microprocessor share the same memory, the two must be synchronized so
that they access that memory during alternate half cycles of the master clock. A 4 MHz oscillator is divided by
four within the 6802 to give the 1 MHz (E) master timing signal. TheE signal from the microprocessor is then
used to synchronize the 2 MHz DOT CLOCK and input to the Character Clock Generator.
15-7.
A raster scan technique is used to generate the character display. The CRT beam is scanned
horizon-tally and vertically across the screen with the beam being modulated by a sequence of pulses. Each
pulse is a dot on the screen whose position is determined by its time of occurrence from the horizontal and
vertical sync pulses. During the horizontal sync the beam is reset to the left edge of the screen and during the
vertical sync it is reset to the top of the screen. Each character field is eight dots wide and eight dots high. There
are 32 character fields across the width of the CRT and 16 character field vertically. Since two horizontal
character fields are used for horizontal sync blanking and one vertical field for vertical sync blanking the total
display area is 30 by 15 characters or 450 characters.
15-1
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