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SECTION 12
AUDIO SYNTHESIZER (AS)
12-1.
General.
Generation, processing, and control of modulation audio is the function of the Audio
Synthesizer module. Three modulation signals, private line, digital private line, and a fixed 1 kHz, are
generated on the board. Processing for external microphone and BNC jack audio inputs as well as sumation of
all modulation sources to form a composite source is provided. Switching of the composite source to the
appropriate modulator completes the function of the Audio Synthesizer. A block diagram of the Audio
Synthesizer is shown in figure 12-1 with its schematic in figure 12-2.
12-2. Private Line Generator.
Private line tones from 10 Hz to 10 kHz in 0.1 Hz increments are synthesized
using a phase accumulative technique. Consider the 360 degrees in a cycle to be divided into 2
20
pieces. A 20
bit digital accumulator incrementing at some fixed rate could then at any instant represent a fixed point in the
360 cycle. That is, if the accumulator was half full it would represent the 180° point and if totally full would
represent the 360° point.
12-3. The number of times per second that the accumulator goes through its complete cycle determines the
output frequency. If the increment rate is fixed, the time required to accumulate 2
20
bits can be changed by
changing the number of bits added at each increment time.
12-4. The PL synthesizer increments at a 104 857.6 Hz rate so that if only one bit were added each time, the
time to complete one cycle would be 10 seconds. Processor loaded control latches determine the number of
bits to be added at each increment time and thus the final output frequency. A 20 Bit Adder adds the control
word to the current word in the 20 bit accumulator Latch. At the next increment time the Adder output is
latched and becomes the next .input to the Adder.
12-5. Conversion of the linear digital output of the 20-Bit Latch accumulator into a sinusoidal dig ita I output is
the function of the Decode ROM. A Digital to Analog (D/A) converter following the ROM converts the
sinusoidal information into a quantized sinewave having a period equal to the cycle time of the 20-Bit Latch
accumulator.
12-6. A band pass fi Iter with a 10 Hz to 1 0 kHz passband filters the quantized waveform to a sinew ave having
less than 1% distortion. The level of the sinewave is processor controllable by a programmable attenuator
having 0, 10, 20, and 30 dB settings. The output of the PL generator is switched with the output of the DPL
generator to give the INT MOD signal.
12-7. DPL Generator. The 23 bit Digital Private Line (DPL) word is generated by the processor from the 3-
digit code. The 23-bit word is then transferred to a serial shift register and clocked out at a 133 Hz rate.
Connecting the output of the shift register back to its input causes the 23-bit word to be continuously repeated.
12-8.
A 133Hz tone from the PL generator is the DPL clock input. For the DPL output mode the tone is gated
to the clock input of the shift register by the Shift Register Control circuit. During the load mode the Shift
Register Control gates a control latch to the shift register input. Twenty three data bits and clock pulses are
then provided by the processor to load the DPL word. At the completion of the load mode, the Shift Register
Control switches back to the output mode to cause the DPL word to be cycled through the shift register at the
133Hz rate.
12-1
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