LG 32SE3B-BE Service Manual page 18

System & DDR
+3.3V_NORMAL
VDDC 1.05V
SPI Boot
/FLASH_WP
NAND
NAND FLASH MEMORY
/F_RB
/PF_OE
/PF_CE0
/PF_CE1
PF_ALE
/PF_WE
/PF_WP
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2015 LG Electronics. Inc. All right reserved.
Only for training and service purposes
STby 3.5V
Normal Power 3.3V
+3.5V_ST
BLM18PG121SN1D
+3.3V_NORMAL
L2
OPT
L1 L3
AVDD_NODIE
BLM18PG121SN1D BLM18PG121SN1D
C2 C5 C8
10uF 0.1uF 0.1uF
L4
BLM18PG121SN1D AVDD_DMPLL
C6 C9
10uF 0.1uF
L5
AVDD_AU33
BLM18PG121SN1D
C3 C7 C10
0.1uF 10uF 0.1uF
+1.10V_VDDC
Normal 2.5V
+1.10V_VDDC
VDDC : 2026mA
+1.10V_VDDC
+1.10V_VDDC
M1A 2.5V inbeded
C41 C42 C43
10uF 0.1uF 0.1uF
10V
+3.5V_ST
+3.5V_ST
+3.3V_NORMAL
SPI_FLASH_MACRONIX OPT
R170
IC14
OPT
0
R168
MX25L8006EM2I-12G
4.7K
+3.5V_ST
C95
CS# VCC 0.1uF
1 8
/SPI_CS
OPT
R167
10K SO/SIO1 HOLD#
2 7
SPI_SDO
WP# SCLK
3 6
SPI_SCK
R169
GND SI/SIO0
33
4 5
SPI_SDI
IC3
H27U1G8F2CTR-BC
+3.3V_NORMAL
NC_1
1 48
NAND_FLASH_1G_HYNIX
NC_2
EAN35669103
2 47
NC_3
3 46
NC_4
4 45
NC_5
R49 R53
1K 3.9K 5 44
NC_6
AR1 6 43
22
R/B
7 42
RE
8 41
CE
9 40
NC_7
10 39
OPT
NC_8
R50
+3.3V_NORMAL C47 11 38
1K
0.1uF VCC_1
12 37
OPT
R41 VSS_1
13 36
1K
NC_9
14 35
R227 NC_10
10K
15 34
READY
CLE
16 33
ALE
17 32
WE
18 31
WP
19 30
AR2
NC_11
22 R46 20 29
R36 1K
NC_12
3.3K 21 28
NC_13
22 27
NC_14
23 26
NC_15
24 25
Parts No.1~300
DDR3 1.5V
VDD33
+1.5V_DDR
L6 AVDD_DDR0:55mA
BLM18PG121SN1D
AVDD_DDR1:55mA
+1.5V_DDR +1.5V_DDR
A-MVREFDQ
CLose to M1A IC
CLose to DDR3
MSTAR DEBUG 4PIN
MSTAR_DEBUG_4P
P2
SMW200-04
+3.5V_ST
R172
0
NC
1
OPT
OPT
GND
R164 2
R165
4.7K
4.7K
SCL
3
RGB_DDC_SCL
SDA
4
RGB_DDC_SDA
+3.3V_NORMAL
NC_29
NC_28
PCM_A[0-7]
NC_27
22
NC_26
AR3
<CHIP Config>
I/O7 PCM_A[7]
(SPI_SDI, PM_LED, PWM_PM)
I/O6 PCM_A[6]
LG-NonOS SB51_ExtSPI 3'b000 51boot from SPI
LG-OS HEMCU_ExtSPI 3'b001 MIPS boot from SPI
I/O5 PCM_A[5]
I/O4 PCM_A[4]
+3.5V_ST
NC_25
NC_24
C48
10uF
NC_23 10V
NAND_FLASH_2G_HYNIX NAND_FLASH_2G_NEW_SKHYNIX
IC3-*1 IC3-*2
VCC_2 H27U2G8F2CTR H27U2G8F2DTR-BD
C49 NC_1 NC_29 NC_1
1 48 1
NC_2 NC_28 NC_2
0.1uF 2 47 2
VSS_2 NC_3 NC_27 NC_3
3 46 3
16V NC_4 NC_26 NC_4
4 45 4
NC_5 I/O7 NC_5
5 44 5
NC_6 I/O6 NC_6
NC_22 6 43 6
R/B I/O5 R/B
7 42 7
RE I/O4 RE
8 41 8
CE NC_25 CE
NC_21 9 40 9
NC_7 NC_24 NC_7
10 39 10
NC_8 NC_23 NC_8
LED_R/BUZZ 11 38 11
VCC_1 VCC_2 VCC_1
12 37 12
NC_20 VSS_1 VSS_2 VSS_1
13 36 13
NC_9 NC_22 NC_9
AR4 14 35 14
NC_10 NC_21 NC_10
PM_LED 15 34 15
CLE NC_20 CLE
I/O3 PCM_A[3] 16 33 16
ALE I/O3 ALE
17 32 17
WE I/O2 WE
18 31 18
SPI_SDI WP I/O1 WP
I/O2 PCM_A[2] 19 30 19
NC_11 I/O0 NC_11
20 29 20
NC_12 NC_19 NC_12
21 28 21
NC_13 NC_18 NC_13
22 27 22
I/O1 PCM_A[1] NC_14 NC_17 NC_14
23 26 23
NC_15 NC_16 NC_15
24 25 24
I/O0 PCM_A[0]
22
NC_19
NC_18
NC_17
NC_16
I2C
PM MODEL OPTION
+3.5V_ST
+3.5V_ST PM_MODEL_OPT_0
- HIGH : LCD
- LOW :: PDP
PM_MODEL_OPT_1
R56 - Not Use (Ready)
10K
LCD
PM_MODEL_OPT_0
R57
10K
PDP
Option : Ripple Check !!!
+1.5V_DDR +1.5V_DDR
A-MVREFCA
OPT OPT OPT OPT OPT OPT OPT OPT
OPT
SK HYNIX 2G DEFAULT
DDR
DDR_1600_1G_HYNIX
IC5
H5TQ1G63EFR-PBC
EAN61829003
M8 N3
A-MVREFCA VREFCA A0
P7
A1
P3
A2
H1 N2
A-MVREFDQ
VREFDQ A3
P8
A4
DDR_EXT P2
R82 A5
L8 R8
ZQ A6
R2
240
+1.5V_DDR A7
1% T8
A8
B2 R3
VDD_1 A9
10V D9 L7
C60 10uF
DDR_EXT
VDD_2 A10/AP
G7 R7
DDR_EXT C61 0.1uF
VDD_3 A11
K2 N7
C62 0.1uF
DDR_EXT
VDD_4 A12/BC
K8 T3
DDR_EXT C63 0.1uF
VDD_5 NC_7
N1
C64 0.1uF
DDR_EXT
VDD_6
N9 M7
DDR_EXT C65 0.1uF
VDD_7 NC_5
R1
DDR_EXT C66 0.1uF
VDD_8
M2
R9
DDR_EXT C67 0.1uF
VDD_9 BA0
N8
DDR_EXT C68 0.1uF
BA1
M3
DDR_EXT C69 0.1uF
BA2
A1
VDDQ_1
A8 J7
VDDQ_2 CK
C1 K7
VDDQ_3 CK
C9 K9
VDDQ_4 CKE
D2
VDDQ_5
E9 L2
VDDQ_6 CS
F1 K1
VDDQ_7 ODT
H2 J3
VDDQ_8 RAS
H9 K3
VDDQ_9 CAS
L3
WE
J1
NC_1
J9 T2
NC_2 RESET
L1
NC_3
L9
NC_4
T7 F3
A-MA14 NC_6 DQSL
G3
DQSL
A9 C7
VSS_1 DQSU
B3 B7
VSS_2 DQSU
E1
VSS_3
G8 E7
VSS_4 DML
J2 D3
VSS_5 DMU
J8
VSS_6
M1 E3
VSS_7 DQL0
M9 F7
DQL1
VSS_8
P1 F2
VSS_9 DQL2
P9 F8
VSS_10 DQL3
T1 H3
NC_29 VSS_11 DQL4
48
NC_28 T9 H8
47
NC_27 VSS_12 DQL5
46
NC_26 G2
45
I/O7
44 DQL6
I/O6
43 H7
I/O5
42 DQL7
I/O4
41 B1
NC_25
40
NC_24 VSSQ_1
39
NC_23 B9 D7
38
VCC_2 VSSQ_2 DQU0
37
VSS_2 D1 C3
36
NC_22
35 VSSQ_3 DQU1
NC_21
34 D8 C8
NC_20
33 VSSQ_4 DQU2
I/O3
32 E2 C2
I/O2
31
I/O1 VSSQ_5 DQU3
30 E8 A7
I/O0
29
NC_19 VSSQ_6 DQU4
28
NC_18 F9 A2
27
NC_17 DQU5
26 VSSQ_7
NC_16 G1 B8
25
VSSQ_8 DQU6
G9 A3
VSSQ_9 DQU7
DDR & System
EEPROM_SDA
EEPROM_SCL
CLOCK_SDA
CLOCK_SCL
DDR_1600_2G_HYNIX DDR_1600_2G_SKHYNIX DDR_SSE
IC5-*1 IC5-*2 IC5-*3
H5TQ2G63DFR-PBC H5TQ2G63FFR-RDC K4B2G1646Q-BCMA
N3 M8 N3 M8 N3 A0 VREFCA M8
P7 A0 VREFCA P7 A0 A1 VREFCA P7 A1
P3 A2 A1 P3 A2 P3 A2
N2 A3 VREFDQ H1 N2 A3 VREFDQ H1 N2 A3 VREFDQ H1
P8 A4 P8 A4 P8 P2 A4
P2 A5 R8 P2 A5 L8 R8 A5 L8
R2 R8 A6 ZQ L8 R2 A6 ZQ R2 A6 ZQ
T8 A7 T8 A7 T8 A7
R3 A8 B2 R3 A8 B2 R3 A8 A9 VDD_1 B2
L7 A9 VDD_1 D9 L7 A10/AP A9 VDD_1 VDD_2 D9 L7 A10/AP VDD_2 D9
R7 A11 A10/AP VDD_2 VDD_3 G7 R7 A11 VDD_3 G7 R7 A11 VDD_3 G7
N7 A12/BC VDD_4 K2 N7 A12/BC VDD_4 K2 N7 A12/BC VDD_4 K2
T3 A13 VDD_5 K8 T3 A13 VDD_5 K8 T3 A13 VDD_5 N1 K8
VDD_6 N1 T7 M7 A14 VDD_6 N1 N9 M7 VDD_6 N9
M7 NC_5 VDD_7 N9 R1 NC_5 VDD_7 R1 NC_5 VDD_7 R1
M2 VDD_8 R9 M2 VDD_8 R9 M2 VDD_8 R9
N8 BA0 VDD_9 N8 BA0 VDD_9 N8 BA0 VDD_9
M3 BA1 M3 BA1 M3 BA1 BA2
A-MA0 BA2 A1 BA2 VDDQ_1 A1 VDDQ_1 A1
J7 CK VDDQ_1 VDDQ_2 A8 J7 CK VDDQ_2 A8 J7 CK VDDQ_2 A8
K7 CK VDDQ_3 C1 K7 CK VDDQ_3 C1 K9 K7 CK VDDQ_3 C9 C1
K9 CKE VDDQ_4 C9 K9 CKE VDDQ_4 C9 D2 CKE VDDQ_4 D2
A-MA1 L2 VDDQ_5 D2 E9 L2 VDDQ_5 E9 L2 VDDQ_5 E9
K1 CS VDDQ_6 F1 K1 CS VDDQ_6 F1 K1 CS VDDQ_6 F1
J3 ODT VDDQ_7 H2 J3 ODT VDDQ_7 H2 J3 ODT VDDQ_7 H2
K3 RAS VDDQ_8 H9 K3 RAS VDDQ_8 H9 K3 CAS RAS VDDQ_9 VDDQ_8 H9
L3 CAS VDDQ_9 L3 CAS WE VDDQ_9 L3 WE
A-MA2 WE NC_1 J1 NC_1 J1 NC_1 J1
T2 RESET NC_2 J9 T2 RESET NC_2 J9 T2 RESET NC_2 J9
NC_3 L1 NC_3 L1 L9 NC_3 L1 L9
NC_4 L9 F3 NC_4 F3 NC_4 T7
A-MA3 G3 F3 DQSL NC_6 T7 G3 DQSL G3 DQSL NC_6
DQSL DQSL DQSL
C7 A9 C7 A9 C7 DQSU VSS_1 A9
B7 DQSU VSS_1 B3 B7 DQSU DQSU VSS_2 VSS_1 B3 B7 DQSU VSS_2 B3
DQSU VSS_3 VSS_2 E1 VSS_3 E1 VSS_3 E1
A-MA4 E7 DML VSS_4 G8 E7 DML VSS_4 G8 E7 DML VSS_4 G8
D3 DMU VSS_5 J2 D3 DMU VSS_5 J2 D3 DMU VSS_5 J2 J8
VSS_6 J8 E3 VSS_6 J8 M1 E3 VSS_6 M1
F7 E3 DQL0 VSS_7 M1 M9 F7 DQL0 VSS_7 M9 F7 DQL0 VSS_7 M9
A-MA5 F2 DQL1 VSS_8 P1 F2 DQL1 VSS_8 P1 F2 DQL1 VSS_8 P1
F8 DQL2 VSS_9 P9 F8 DQL2 VSS_9 P9 F8 DQL2 VSS_9 P9
H3 DQL3 VSS_10 T1 H3 DQL4 DQL3 VSS_10 VSS_11 T1 H3 DQL3 DQL4 VSS_10 VSS_11 T1
H8 DQL4 VSS_11 T9 H8 DQL5 VSS_12 T9 H8 DQL5 VSS_12 T9
G2 DQL5 DQL6 VSS_12 G2 DQL6 G2 DQL6
A-MA6 H7 DQL7 H7 DQL7 H7 DQL7 B1
VSSQ_1 B1 D7 VSSQ_1 B1 B9 D7 VSSQ_1 B9
C3 D7 DQU0 VSSQ_2 D1 B9 C3 DQU0 VSSQ_2 D1 C3 DQU0 VSSQ_2 D1
C8 DQU1 VSSQ_3 D8 C8 DQU1 VSSQ_3 D8 C8 DQU1 VSSQ_3 D8
A-MA7 C2 DQU2 VSSQ_4 E2 C2 DQU2 VSSQ_4 E2 C2 DQU2 VSSQ_4 E2
A7 DQU3 VSSQ_5 E8 A7 DQU3 VSSQ_5 E8 A7 DQU4 DQU3 VSSQ_5 VSSQ_6 E8
A2 DQU4 VSSQ_6 F9 A2 DQU4 DQU5 VSSQ_7 VSSQ_6 F9 A2 DQU5 VSSQ_7 F9
B8 DQU6 DQU5 VSSQ_8 VSSQ_7 G1 B8 DQU6 VSSQ_8 G1 B8 DQU6 VSSQ_8 G1
A3 DQU7 VSSQ_9 G9 A3 DQU7 VSSQ_9 G9 A3 DQU7 VSSQ_9 G9
A-MA8
A-MA9
A-MA10
A-MA11
A-MA12
A-MA13
A-MBA0 A-MCK
A-MBA1
DDR_EXT
A-MBA2
C70
0.01uF
50V
A-MCKE
A-MCKB
A/B_DDR3_CS
A-MODT
A-MRASB +1.5V_DDR
A-MCASB DDR_EXT
R84
A-MWEB
10K
A-MRESETB
A-MDQSL
A-MDQSLB
A-MDQSU
A-MDQSUB
A-MDML
A-MDMU
A-MDQL0
A-MDQL1
A-MDQL2
A-MDQL3
A-MDQL4
A-MDQL5
A-MDQL6
A-MDQL7
A-MDQU0
A-MDQU1
A-MDQU2
A-MDQU3
A-MDQU4
A-MDQU5
A-MDQU6
A-MDQU7
LS33B 14/10/09
LGE Internal Use Only