Mitsubishi Electric MELCEC Q Series User Manual page 219

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APPENDICES
Number
Name
Active step
M9180
sampling trace
complete flag
Active step
M9181
sampling trace
execution flag
Active step
*2
sampling trace
M9182
enable
Operation
*2
output at block
M9196
stop
M9197
Fuse blow, I/O
verify error
display
switching
M9198
Data recovery
of online
M9199
sampling trace /
status latch
*:
Usable with AnN and AnA which are compatible with SFC.
For the AnN and AnA which are compatible with SFC, refer to the MELSAP-II Programming Manual.
Table App.2.1 Special Relay List (continued)
Description
• Turned on when sampling trace of all specified
OFF:Trace start
ON: Trace complete
OFF:Trace not executed.
• Turned on when sampling trace is being executed.
ON: Trace being
executed.
• Selects sampling trace execution enable/disable.
OFF:Trace disable/
suspend
ON: Trace enable
• Selects the operation output when block stop is
OFF:Coil output off
ON: Coil output on
I/O numbers
to be
displayed
• Switches I/O numbers in the fuse blow module
OFF OFF X/Y0 to 7F0
X/Y800 to
ON
OFF
FF0
X/Y1000 to
OFF
ON
17F0
X/Y1800 to
ON
ON
1FF0
• When sampling trace / status latch is executed,
OFF:No data recovery
ON: Data recovery
• Turn on M9199 to execute again.
Details
blocks is completed. Turned off when sampling
trace is started.
Turned off when sampling trace is completed or
suspended.
ON:
Sampling trace execution is enabled.
OFF: Sampling trace execution is disabled.
If turned off during sampling trace
execution, trace is suspended.
executed.
ON:
Retains the on or off status of the coil being
used by using operation output of the step
being executed at block stop.
OFF: All coil outputs are turned off. (Operation
output by the SET instruction is retained
regardless of the on or off status of M9196.)
storage registers (D9100 to D9107) and I/O
module verify error storage registers (D9116 to
D9123) according to the combination of on and off
states of M9197 and M9198.
the setting data stored in the CPU module is
recovered to enable restart.
(There is no need to write data with the peripheral
device.)
App - 25
Applicable CPU
Usable with AnN*,
AnA*, AnU,
A2AS, QCPU-A
(A Mode), A2C,
A0J2H, AnS,
AnSH, A1FX and
A52G.
Usable with AnN*,
AnA*, AnU,
A2AS, QCPU-A
(A Mode), A2C,
A0J2H, AnS,
AnSH, A1FX and
A52G.
Usable with AnN*,
AnA*, AnU,
A2AS, QCPU-A
(A Mode), A2C,
A0J2H, AnS,
AnSH, A1FX and
A52G.
Usable with AnN*,
AnA*, AnU,
A2AS, QCPU-A
(A Mode), A2C,
A0J2H, AnS,
AnSH, A1FX and
A52G.
Usable with AnU,
A2AS and QCPU-
A (A Mode)
Usable with AnU,
A2AS and QCPU-
A (A Mode)

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