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Block Diagram
1
Note that the
switch logic in the VMEchip2 is not used. The
ABORT
GPI inputs to the VMEchip2 which are located at $FFF40088 bits 7-
0 are not used. The
switch interrupt is integrated into the
ABORT
MC2chip ASIC at location $FFF42043. The GPI inputs are
integrated into the MC2chip ASIC at location $FFF4202C bits 23-16.
I/O Interfaces
The MVME162LX provides onboard I/O for many system
applications. The I/O functions include serial ports, IndustryPack
(IP) interfaces, an optional LAN Ethernet transceiver interface, and
an optional SCSI mass storage interface.
Serial Communications Interface
The MVME162LX uses two Zilog Z85230 serial port controllers to
implement the four serial communications interfaces. Each
interface supports CTS, DCD, RTS, and DTR control signals, as well
as the TXD and RXD transmit/receive data signals. Because the
serial clocks are omitted in the MVME162LX implementation, serial
communications are strictly asynchronous. The MVME162LX
hardware supports serial baud rates of 110b/s to 38.4Kb/s.
The Z85230 supplies an interrupt vector during interrupt
acknowledge cycles. The vector is modified based upon the
interrupt source within the Z85230. Interrupt request levels are
programmed via the MC2chip. Refer to the Z85230 data sheet listed
in this chapter, and to the MC2chip Programming Model in the
MVME162LX Embedded Controller Programmer's Reference Guide, for
information.
The Z85230s are interfaced as DTE (data terminal equipment) with
EIA-232-D signal levels. The four serial ports are routed to four RJ-
45 connectors on the MVME162LX front panel.
1-21
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