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List Of I/o Signals - Mitsubishi Electric MELSEC-Q Series User Manual

Melsec-q/l anywireaslink master module.
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3.4

List of I/O Signals

The following table lists the signals input or output between the CPU module and the master module.
For details on the I/O signals, refer to Page 101, Appendix 1.
Signal direction: Master module to CPU module
Device number
Xn0
Xn1
Xn2
Xn3
Xn4
Xn5 to XnF
X(n+1)0
X(n+1)1
X(n+1)2
X(n+1)3
X(n+1)4
X(n+1)5 to X(n+1)F
Signal name
Module READY
DP/DN short error
Use prohibited
Transmission cable voltage drop
error
DP/DN disconnection error
Use prohibited
Slave module alarm signal
Parameter access completion
flag
Parameter access error
Use prohibited
Automatic address detection flag
Use prohibited
Signal direction: CPU module to master module
Device number
Yn0
Error flag clear command
Automatic address detection
Yn1
command
Yn2 to YnF
Use prohibited
Parameter access request
Y(n+1)0
command for the slave module
Parameter batch read command
Y(n+1)1
for the slave module
Parameter batch write command
Y(n+1)2
for the slave module
Y(n+1)3 to Y(n+1)F
Use prohibited
CHAPTER 3 SPECIFICATIONS
Signal name
33
3

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