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Communication Performance - Mitsubishi Electric MELSEC-Q Series User Manual

Melsec-q/l anywireaslink master module.
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3.2.3

Communication performance

(1) Transmission cycle time
The transmission cycle time is the time required for the master module and all the slave modules to update I/O
data.
The transmission cycle time of the master module is listed in the table below.
Number of
transmission points
One transmission
cycle time
Remark
● The transmission delay time is a value between one- and two-transmission cycle time.
● To ensure the response to the input signal, provide an input signal that is longer than two-transmission cycle time.
(2) Effects of the double check system
(a) Input
Unless the same data is received twice successively on the master module side, the input area data is not
updated.
A minimum of one-transmission cycle time and a maximum of two-transmission cycle time are required as the
data response time.
Therefore, when an input signal is shorter than two-transmission cycle time, the input data may not be captured
depending on the timing.
To ensure the response, provide an input signal that is longer than two-transmission cycle time.
Minimum data
response time
Maximum data
response time
(b) Output
As the double check is performed on the slave module side, the time required is the same as that for input,
namely a minimum of one-transmission cycle time and a maximum of two-transmission cycle time.
64 points (32 input
128 points (64 input
points, 32 output
points, 64 output
points)
points)
2.3ms
3.5ms
Sampling timing
Minimum one-transmission cycle time
Input data change
Sampling timing
Maximum two-transmission cycle time
Input data change
256 points (128 input
points, 128 output points)
5.9ms
Sampling timing
Input data update
Sampling timing
Sampling timing
Input data update
CHAPTER 3 SPECIFICATIONS
512 points (256 input
points, 256 output points)
10.6ms
29
3

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