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Tews Technologies TPMC682-10 User Manual

3 x 16 bit i/o ports with 512 word fifo and handshake
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The Embedded I/O Company
512 Word FIFO and Handshake
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7
25469 Halstenbek, Germany
www.tews.com
TPMC682
3 x 16 bit I/O Ports with
Version 1.0
User Manual
Issue 1.1
September 2006
D76682800
Phone: +49-(0)4101-4058-0
Fax: +49-(0)4101-4058-19
e-mail: info@tews.com
TEWS TECHNOLOGIES LLC
9190 Double Diamond Parkway,
Suite 127, Reno, NV 89521, USA
www.tews.com
Phone: +1 (775) 850 5830
Fax: +1 (775) 201 0347
e-mail: usasales@tews.com

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  • Page 1 3 x 16 bit I/O Ports with 512 Word FIFO and Handshake Version 1.0 User Manual Issue 1.1 September 2006 D76682800 TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC Am Bahnhof 7 Phone: +49-(0)4101-4058-0 9190 Double Diamond Parkway, Phone: +1 (775) 850 5830 25469 Halstenbek, Germany...
  • Page 2 However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice. TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein.
  • Page 3 Issue Description Date First Issue April 2005 New address TEWS LLC September 2006 TPMC682 User Manual Issue 1.1 Page 3 of 36...

  • Page 4: Table Of Contents

    Table of Contents PRODUCT DESCRIPTION ..................6 TECHNICAL SPECIFICATION................... 7 HANDSHAKE MODE ....................8 LOCAL SPACE ADDRESSING................11 4.1 PCI9030 Local Space Configuration ...................11 4.2 FPGA Control Register Space .....................12 4.2.1 Interrupt and FIFO Control Register (IFCR; 0x00) .............13 4.2.2 Port Data Direction Register (PDDR;...
  • Page 5 Table of Figures FIGURE 1-1 : BLOCK DIAGRAM........................6 FIGURE 2-1 : TECHNICAL SPECIFICATION....................7 FIGURE 3-1 : INPUT TRANSFER TIMING DIAGRAM ..................9 FIGURE 3-2 : OUTPUT TRANSFER TIMING DIAGRAM................10 FIGURE 4-1 : PCI9030 LOCAL SPACE CONFIGURATION ................11 FIGURE 4-2 : CONTROL REGISTER SPACE ....................12 FIGURE 4-3 : INTERRUPT AND FIFO CONTROL REGISTER (IFCR) ............13 FIGURE 4-4 : PORT DATA DIRECTION REGISTER (PDDR) ...............13 FIGURE 4-5 : HANDSHAKE STATUS AND CONTROL REGISTER 2 (HSCR2) ..........14...

  • Page 6: Product Description

    1 Product Description The TPMC682 is a standard single-width 32 bit PMC with three 16 bit TTL digital input/output lines controlled by handshake signals. These handshake signals run over an additional 8 bit input and an 8 bit output port. Interlocked or pulsed handshake protocol is provided. Each I/O port has a 512 words deep FIFO.

  • Page 7: Technical Specification

    2 Technical Specification PMC Interface Mechanical Interface PCI Mezzanine Card (PMC) Interface Single Size Electrical Interface PCI Rev. 2.1 compliant 33 MHz / 32 bit PCI 3.3V and 5V PCI Signaling Voltage On Board Devices PCI Target Chip PCI9030 (PLX Technology) Local Control Logic FPGA Spartan2 XC2S100-5 FG256 I (Xilinx) I/O Interface...

  • Page 8: Handshake Mode

    3 Handshake Mode There are three 16 bit ports available (Port 0 - 2), input and output transfers are buffered by FIFOs, each 512 words deep. Buffering allows orderly transfers by using the handshake pins in one of two programmable protocols. Use of buffering is most beneficial in situations where a peripheral device and the computer system are capable of transferring data at roughly the same speed.

  • Page 9: Figure 3-1 : Input Transfer Timing Diagram

    A timeout function can signal when no data was received for a specified timeout period. It is realized by a counter which is clocked with 1/33 of the PCI clock frequency, normally about 1 MHz (or 1µs period time). The timeout period is specified by the 16 bit preload value of the timeout (downward-) counter in the Timeout Counter Preload Registers TCPR0/1/2, i.e.: the maximum timeout period is about 65ms.

  • Page 10: Figure 3-2 : Output Transfer Timing Diagram

    The typical delay time between a falling edge on H1 (H3/H5) and the next falling edge on H2 (H4/H6) signaling new valid output data, is about 180ns. Figure 3-2 : Output Transfer Timing Diagram TPMC682 User Manual Issue 1.1 Page 10 of 36...

  • Page 11: Local Space Addressing

    4 Local Space Addressing 4.1 PCI9030 Local Space Configuration The local on board addressable regions are accessed from the PCI side by using the PCI9030 local spaces. PCI9030 PCI9030 Size Port Endian Description Space Width Mode Local PCI Base Address (Byte) Mapping Space...

  • Page 12: Fpga Control Register Space

    4.2 FPGA Control Register Space PCI Base Address: PCI9030 PCI Base Address 2 (Offset 0x18 in PCI Configuration Space). Size Offset to PCI Register Name Base Address 2 (Bit) 0x00 INTERRUPT AND FIFO CONTROL REGISTER (IFCR) 0x04 PORT DATA DIRECTION REGISTER (PDDR) 0x08 ...

  • Page 13: Interrupt And Fifo Control Register (Ifcr; 0X00)

    4.2.1 Interrupt and FIFO Control Register (IFCR; 0x00) Reset Symbol Description Access Value 31..8 Reserved (0 for reads) FIFO_FLUSH FIFO Flush Request 0 : no FIFO Flush Request 1 : Flush all FIFOs (bit is automatically reset) 6..1 Reserved (0 for reads) GLOB_INT_EN Global Interrupt Enable 0 : Interrupts disabled...

  • Page 14: Handshake Status And Control Register 2 (Hscr2; 0X11)

    4.2.3 Handshake Status and Control Register 2 (HSCR2; 0x11) See chapter “Handshake Mode” for a description of the mode and the configuration bits in the Handshake Status and Control Registers. Reset Symbol Description Access Value FIFO_STATUS2 FIFO Status Flag 0 : FIFO level within threshold of FTHR2 1 : FIFO level exceeds threshold of FTHR2 6..5 PORT2_HS...

  • Page 15: Handshake Status And Control Register 1 (Hscr1; 0X12)

    4.2.4 Handshake Status and Control Register 1 (HSCR1; 0x12) Reset Symbol Description Access Value FIFO_STATUS1 FIFO Status Flag 0 : FIFO level within threshold of FTHR1 1 : FIFO level exceeds threshold of FTHR1 6..5 PORT1_HS H4 Handshake Output Protocol 00 : none 10 : Interlocked Handshake Protocol 11 : Pulsed Handshake Protocol...

  • Page 16: Handshake Status And Control Register 0 (Hscr0; 0X13)

    4.2.5 Handshake Status and Control Register 0 (HSCR0; 0x13) Reset Symbol Description Access Value FIFO_STATUS0 FIFO Status Flag 0 : FIFO level within threshold of FTHR0 1 : FIFO level exceeds threshold of FTHR0 6..5 PORT0_HS H2 Handshake Output Protocol 00 : None 10 : Interlocked Handshake Protocol 11 : Pulsed Handshake Protocol...

  • Page 17: Timeout Counter Preload Register 2 (Tcpr2; 0X14)

    4.2.6 Timeout Counter Preload Register 2 (TCPR2; 0x14) Reset Symbol Description Access Value 31..16 Reserved (0 for reads) 15..0 TOUT_CNTRPREL2 Timeout Value for Read Access 0x00FF (multiply value with 33 times the PCI cycle time for resulting timeout delay time) Figure 4-8 : FIFO Threshold Register 2 (FTHR2) 4.2.7 Timeout Counter Preload Register 1 (TCPR1;...

  • Page 18: Fifo Data Counter Register 2 (Fdcr2; 0X20)

    4.2.9 FIFO Data Counter Register 2 (FDCR2; 0x20) Reset Symbol Description Access Value 31..10 Reserved (0 for reads) 9..0 FIFO_CNTR2 Amount of data words in FIFO 2 0x000 Figure 4-11: FIFO Data Counter Register 2 (FDCR2) 4.2.10 FIFO Data Counter Register 1 (FDCR1; 0x24) Reset Symbol Description...

  • Page 19: Fifo Threshold Register 2 (Fthr2; 0X30)

    4.2.12 FIFO Threshold Register 2 (FTHR2; 0x30) Reset Symbol Description Access Value 31..10 Reserved (0 for reads) 9..0 FIFO_FTR2 Threshold of FIFO 2 for setting of FIFO_STATUS2 0x040 Figure 4-14: FIFO Threshold Register 2 (FTHR2) 4.2.13 FIFO Threshold Register 1 (FTHR1; 0x34) Reset Symbol Description...

  • Page 20: Fpga Port Register Space

    4.3 FPGA Port Register Space PCI Base Address: PCI9030 PCI Base Address 3 (Offset 0x1C in PCI Configuration Space). Access Size Offset to PCI Register Name Width Base Address 3 (Bit) (Bit) HS-PORT 2 DATA REGISTER (PDR2) 16/32 (or 0x2) HS-PORT 1 DATA REGISTER (PDR1) 16/32 (or 0x6)

  • Page 21: Hs-Port Data Register 2 (Pdr2; 0X0 Or 0X2)

    4.3.1 HS-Port Data Register 2 (PDR2; 0x0 or 0x2) Reset Symbol Description Access Value PORT2_BIT_15 PORT2_BIT_14 PORT2_BIT_13 PORT2_BIT_12 PORT2_BIT_11 PORT2_BIT_10 PORT2_BIT_9 PORT2_BIT_8 Port 2 bit 0-15 PORT2_BIT_7 PORT2_BIT_6 PORT2_BIT_5 PORT2_BIT_4 PORT2_BIT_3 PORT2_BIT_2 PORT2_BIT_1 PORT2_BIT_0 Figure 4-18: HS-Port Data Register 2 For performance reasons it might be useful to read/write 32 bit lwords at once over the PCI bus to the FIFOs.

  • Page 22: Figure 4-19: Example Of A 32 Bit Port Data Register Write Access

    Figure 4-19: Example of a 32 Bit Port Data Register Write Access TPMC682 User Manual Issue 1.1 Page 22 of 36...

  • Page 23: Hs-Port Data Register 1 (Pdr1; 0X4 Or 0X6)

    4.3.2 HS-Port Data Register 1 (PDR1; 0x4 or 0x6) Reset Symbol Description Access Value PORT1_BIT_15 PORT1_BIT_14 PORT1_BIT_13 PORT1_BIT_12 PORT1_BIT_11 PORT1_BIT_10 PORT1_BIT_9 PORT1_BIT_8 Port 1 bit 0-15 PORT1_BIT_7 PORT1_BIT_6 PORT1_BIT_5 PORT1_BIT_4 PORT1_BIT_3 PORT1_BIT_2 PORT1_BIT_1 PORT1_BIT_0 Figure 4-20: HS-Port Data Register 1 4.3.3 HS-Port Data Register 0 (PDR0;...

  • Page 24: Port Data Register 5 (Pdr5; 0Xc)

    4.3.4 Port Data Register 5 (PDR5; 0xC) Reset Symbol Description Access Value PORT5_BIT_7 PORT5_BIT_6 PORT5_BIT_5 Port 5 bit 3-7 Data PORT5_BIT_4 PORT5_BIT_3 PORT5_BIT_2 Handshake output signal H6 PORT5_BIT_1 Handshake output signal H4 PORT5_BIT_0 Handshake output signal H2 Figure 4-22: Port Data Register 5 (PDR5) 4.3.5 Port Data Register 4 (PDR4;...

  • Page 25: Pci9030 Target Chip

    5 PCI9030 Target Chip 5.1 PCI Configuration Registers (PCR) 5.1.1 PCI9030 Header PCI CFG Write ‘0’ to all unused (Reserved) bits Initial Values Register writeable (Hex Values) Address 31 0x00 Device ID Vendor ID 02AA 1498 0x04 Status Command 0280 0000 0x08 Class Code Revision ID...

  • Page 26: Pci Base Address Initialization

    5.1.2 PCI Base Address Initialization PCI Base Address Initialization is scope of the PCI host software. PCI9030 PCI Base Address Initialization: 1. Write 0xFFFF_FFFF to the PCI9030 PCI Base Address Register. 2. Read back the PCI9030 PCI Base Address Register. 3.

  • Page 27: Local Configuration Register (Lcr)

    5.2 Local Configuration Register (LCR) After reset, the PCI9030 Local Configuration Registers are loaded from the on board serial configuration EEPROM. The PCI base address for the PCI9030 Local Configuration Registers is PCI9030 PCI Base Address 0 (PCI Memory Space) (Offset 0x10 in the PCI9030 PCI Configuration Register Space) or PCI9030 PCI Base Address 1 (PCI I/O Space) (Offset 0x14 in the PCI9030 PCI Configuration Register Space).

  • Page 28: Configuration Eeprom

    5.3 Configuration EEPROM After power-on or PCI reset the PCI9030 loads initial configuration register data from the on board configuration EEPROM. The configuration EEPROM contains the following configuration data: • Address 0x00 to 0x27 : PCI9030 PCI Configuration Register Values •...

  • Page 29: Local Software Reset

    5.4 Local Software Reset The PCI9030 Local Reset Output LRESETo# is used to reset the on board local logic. The PCI9030 local reset is active during PCI reset or if the PCI Adapter Software Reset bit is set in the PCI9030 local configuration register CNTRL (offset 0x50).

  • Page 30: Configuration Hints

    6 Configuration Hints 6.1 Big / Little Endian PCI – Bus (Little Endian) Byte 0 AD[7..0] Byte 1 AD[15..8] Byte 2 AD[23..16] Byte 3 AD[31..24] Every Local Address Space (0...3) and the Expansion ROM Space can be programmed to operate in Big or Little Endian Mode.
  • Page 31 Standard use of the TPMC682 design: Local Address Space 0 32 bit bus in Big Endian Mode Local Address Space 1 16 bit bus in Big Endian Mode Local Address Space 2 not used Local Address Space 3 not used Expansion ROM Space not used To change the Endian Mode use the Local Configuration Registers for the corresponding Space.

  • Page 32: Installation

    7 Installation 7.1 I/O Circuit The 64 I/O lines are realized with 8 x 74AHCT245 8 bit bus transceivers, a serial resistor and an array for ESD and overvoltage protection (see figure below “I/O Circuitry”). The maximum output current per line is +/- 8mA.

  • Page 33: Back I/O Configuration

    7.2 Back I/O Configuration The configuration of P14 64 pin Mezzanine “Back I/O” connector pins [57..64] can be changed between ground or port 2 [8..15] signals by zero ohm resistors. For removing zero ohm resistors, work on a grounded, static free work surface. The pads of the zero ohm resistors allow making a direct solder connection between the pads after removing the zero ohm resistors.

  • Page 34: Figure 7-4 : Jumper Positions For Back I/O Options

    Back I/O Pin Signal Jumper Position ground (default) Port 2 I/O Line 8 ground (default) Port 2 I/O Line 9 ground (default) Port 2 I/O Line 10 ground (default) Port 2 I/O Line 11 ground (default) Port 2 I/O Line 12 ground (default) Port 2 I/O Line 13 ground (default)

  • Page 35: Pin Assignment - I/O Connector

    8 Pin Assignment – I/O Connector 8.1 Back I/O P14 See chapter "Back I/O Configuration". Signal Signal Port 0, I/O Line 0 Port 4 I/O Line 0 (H1) Port 0, I/O Line 1 Port 4 I/O Line 1 (H3) Port 0, I/O Line 2 Port 4 I/O Line 2 (H5) Port 0, I/O Line 3 Port 4 I/O Line 3...

  • Page 36: Front Panel I/O

    8.2 Front Panel I/O All I/O ports are available on the HD68 SCSI 3-type front panel connector. Signal Signal Port 0, I/O Line 0 Port 4 I/O Line 2 (H5) Port 0, I/O Line 1 Port 4 I/O Line 3 Port 0, I/O Line 2 Port 4 I/O Line 4 Port 0, I/O Line 3...

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