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Summary of Contents for Microsemi MiV_RV32IMAF_L1_AHB
- Page 1 HB0801 MiV_RV32IMAF_L1_AHB V2.0 Handbook 11 2017...
- Page 2 Microsemi. It is the Buyer’s responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer.
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Page 3: Revision History
HB0801: MiV_RV32IMAF_L1_AHB V2.0 Handbook Revision History The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication. 1.1 Release 1.0 Revision 1.0 is the first production-level publication of this document. Created for MiV_RV32IMAF_L1_AHB v2.0. -
Page 4: Table Of Contents
6 Tool Flow ..........................17 License ..............................17 6.1.1 RTL ............................. 17 SmartDesign ............................. 17 Configuring MiV_RV32IMAF_L1_AHB in SmartDesign ................17 Debugging ..............................18 Simulation Flows ............................18 Synthesis in Libero ........................... 19 Place-and-Route in Libero ........................19 7 System Integration ......................... 20 Example System ............................ - Page 5 HB0801: MiV_RV32IMAF_L1_AHB V2.0 Handbook 8 Design Constraints ......................... 22 9 SoftConsole ..........................24 10 Known Issues .......................... 25 10.1 Reset/Power Cycle the Target Hardware before each Debug Session ............. 25 50200801 Handbook 1...
- Page 6 Figure 1 MiV_RV32IMAF_L1_AHB Block Diagram ......................8 Figure 2 MiV_RV32IMAF_L1_AHB Block Diagram ....................... 11 Figure 3 Example Five Stage Pipelined Architecture ....................12 Figure 4 SmartDesign MiV_RV32IMAF_L1_AHB Instance View .................. 17 Figure 5 Configuring MiV_RV32IMAF_L1_AHB in SmartDesign .................. 18 Figure 6 RTG4 Example Simulation Subsystem......................18 Figure 7 MiV_RV32IMAF_L1_AHB Example System ....................
- Page 7 Table 1 Device Utilization and Performance ......................... 9 Table 2 MiV_RV32IMAF_L1_AHB Architecture ......................10 Table 3 Example Pipeline Timing ..........................12 Table 4 MiV_RV32IMAF_L1_AHB Configuration Options .................... 14 Table 5 MiV_RV32IMAF_L1_AHB I/O Signals ......................14 Table 6 Physical Memory Map (from E3 Coreplex Series) ................... 16...
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Page 8: Introduction
The MiV_RV32IMAF_L1_AHB is a softcore processor designed to implement the RISC-V instruction set for use in Microsemi FPGAs. The processor is based on the Coreplex E31 designed by SiFive, containing a high-performance single-issue, in-order execution pipeline E31 32-bit RISC-V core. The core includes an industry-standard JTAG interface to facilitate debug access, along with separate AHB bus interfaces for memory access and support for 31 dedicated interrupt ports. -
Page 9: Features
• Two external AHB interfaces for IO and memory. Core Version This Handbook applies to MiV_RV32IMAF_L1_AHB version 2.0. Note: There are two accompanying manuals for this core: • The RISC-V Instruction Set Manual, Volume 1, User Level ISA, Version 2.1 •... -
Page 10: Functional Description
HB0801: MiV_RV32IMAF_L1_AHB V2.0 Handbook Functional Description MiV_RV32IMAF_L1_AHB Architecture Table 2 MiV_RV32IMAF_L1_AHB Architecture Parameter Value Units Notes ISA Support RV32IMAF Cores Harts/Cores Branch prediction None Static Not Taken Multiplier occupancy cycles 2-bit/cycles iterative multiply I-cache size I-cache associativity direct-mapped I-cache line-size... -
Page 11: Miv_Rv32Imaf_L1_Ahb Processor Core
AHB MMIO I/F AHB Memory I/F MiV_RV32IMAF_L1_AHB Processor Core MiV_RV32IMAF_L1_AHB is based on the E31 Coreplex Core by SiFive. The core provides a single hardware thread (or hart) supporting the RISC-V standard RV32IMAF ISA and machine-mode privileged architecture. Pipelined Architecture MiV_RV32IMAF_L1_AHB provides a high-performance single-issue in-order 32-bit execution pipeline, with a peak sustainable execution rate of one instruction per clock cycle. -
Page 12: Memory System
Table 3 Example Pipeline Timing Memory System MiV_RV32IMAF_L1_AHB memory system supports configurable split first-level instruction and data caches with full support for hardware cache flushing, as well as uncached memory accesses. External connections are provided for both cached and uncached TileLink fabrics. -
Page 13: External Ahb Interfaces
HB0801: MiV_RV32IMAF_L1_AHB V2.0 Handbook External AHB Interfaces MiV_RV32IMAF_L1_AHB includes two external AHB interfaces, bridged from the internal TileLink interfaces. The AHB memory interface is used by the cache controller to refill the instruction and data caches. The AHB I/O interface is used for uncached accesses to I/O peripherals. -
Page 14: Interface
Interface Configuration Parameters 4.1.1 MiV_RV32IMAF_L1_AHB Configurable Options There are two configurable options that apply to MiV_RV32IMAF_L1_AHB as shown in Table 4. If a configuration other than the default is required, use the configuration dialog box in SmartDesign to select appropriate values for the configurable options. - Page 15 HB0801: MiV_RV32IMAF_L1_AHB V2.0 Handbook Port Name Width Direction Description External Interrupts Signals External interrupts from off-chip or peripheral sources. These are level-based interrupt signals. AHB Cached Memory Bus Master Interface AHB_MST_MEM_HLOCK AHB_MST_MEM_HTRANS AHB_MST_MEM_HSEL AHB_MST_MEM_HWRITE AHB_MST_MEM_HADDR AHB_MST_MEM_HSIZE AHB Master interface for cached memory accesses.
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Page 16: Register Map And Descriptions
HB0801: MiV_RV32IMAF_L1_AHB V2.0 Handbook Register Map and Descriptions Table 6 Physical Memory Map (from E3 Coreplex Series) Base Description 0x0000_0000 0x0000_00FF Reserved 0x0000_0100 Clear debug interrupt to component 0x0000_0104 Set debug interrupt to component Debug Area(4 KiB) 0x0000_0108 Clear halt notification from component... -
Page 17: Tool Flow
Allowing the core to be instantiated with SmartDesign. Simulation, Synthesis, and Layout can be performed within Libero SoC. SmartDesign MiV_RV32IMAF_L1_AHB is preinstalled in SmartDesign IP Deployment design environment. For more information on using SmartDesign to instantiate and generate cores, refer to the Using DirectCore in Libero®... -
Page 18: 6.4 Debugging
The user testbench for MiV_RV32IMAF_L1_AHB is not included in this release. The MiV_RV32IMAF_L1_AHB RTL can be used to simulate the processor executing a program using a standard Libero generated HDL testbench. An example subsystem for RTG4 is as shown in... -
Page 19: Synthesis In Libero
To run synthesis on the core, set the SmartDesign sheet as the design root and click Synthesis in Libero SoC. Place-and-Route in Libero After the design is synthesized, run the compilation and the place and-route tools. Click Layout in the Libero SoC to invoke Designer. MiV_RV32IMAF_L1_AHB requires the place-and-route multi-seed settings set to 5. 50200801 Handbook 1... -
Page 20: System Integration
AND the LOCK output of the CCC with the push button reset to generate the RST input for MiV_RV32IMAF_L1_AHB. However, this results in the reset being deasserted when the CLK comes up, hence the reset assertion is not clocked through the sequential reset elements and goes unnoticed most commonly leading to the processor locking-up. -
Page 21: Trst
HDL type whilst unchecking the option to Initialize file with standard template. Copy and paste the Verilog code snippet above into this file and save the changes. From the Design Hierarchy tab drag and drop the file into the SmartDesign sheet containing the MiV_RV32IMAF_L1_AHB instance and connect up the pins as shown above. -
Page 22: Design Constraints
Double-click Constraints > Manage Constraints in the Design Flow window and click the Timing tab. Assuming that the system clock used to clock MiV_RV32IMAF_L1_AHB is sourced from a PLL, select Derive to automatically create a constraints file containing the PLL constraints. Select Yes when prompted to allow the constraints to be automatically included for Synthesis, Place-and- Route, and Timing Verification stages. - Page 23 HB0801: MiV_RV32IMAF_L1_AHB V2.0 Handbook Where: PLL_GEN_CLK is the name applied to the create_generated_clock constraint derived in step 1 above. 5. Next constraints must be applied to the Floating Point Unit between the source clock and the following signals: i. MIV_RV32IMAF_L1_AHB_0/ChiselTop0/tile/rocket/fpuOpt/sfma/_T_28_data* ii.
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Page 24: Softconsole
9 SoftConsole SoftConsole Version 5.2 is required to use MiV_RV32IMAF_L1_AHB. Each SoftConsole project requires the Hardware Abstraction Layer (HAL) version 2.1 or greater. The SoftConsole Release Notes details how to set up a project for the MiV_RV32IMAF_L1_AHB core. 50200801 Handbook 1... -
Page 25: 10 Known Issues
HB0801: MiV_RV32IMAF_L1_AHB V2.0 Handbook 10 Known Issues 10.1 Reset/Power Cycle the Target Hardware before each Debug Session At the moment, the debugger cannot effect a suitable Mi-V RISC-V CPU/SoC reset at the start of each debug session so one debug session may be impacted by what went before – for example, a previous debug session leaves the CPU in an ISR and a subsequent debug session does not behave as expected because of this.
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