Mitsubishi Electric MELSEC iQ-R Series User Manual page 147

IO device data exchange management setting area
■IO device data exchange management setting area (Un\G17009 to Un\G17016)
Set to start or stop the I/O data exchange with each IO device.
The setting of this area is applied to the IO device where I/O data exchange manual start is set in 'IO device data exchange
start method setting area' (Un\G17001 to Un\G17008).
By setting 'IO device data exchange management execution request' (Un\G17017 to Un\G17024) after setting this area, the
start/stop of the I/O data exchange with each IO device is controlled.
• 0: Stop I/O data exchange with each IO device
• 1: Start I/O data exchange with each IO device
Address b15 b14 b13
Un\G17009 15 14 13

Un\G17016 127 126 125
Each number in the table represents an IO device ID. Each bit corresponds to the IO device ID. For IO device IDs, refer to the
following.
Page 82 [General Configuration] tab
IO device data exchange management execution request
■IO device data exchange management execution request (Un\G17017 to Un\G17024)
Set whether or not to apply the setting of 'IO device data exchange management setting area' (Un\G17009 to Un\G17016).
After setting 'IO device data exchange management setting area' (Un\G17009 to Un\G17016), set 1 in this area to control the
start/stop of the I/O data exchange with each IO device.
The setting of this area is applied to the IO device where I/O data exchange manual start is set in 'IO device data exchange
start method setting area' (Un\G17001 to Un\G17008).
• 0: Do not apply the setting of 'IO device data exchange management setting area' (Un\G17009 to Un\G17016)
• 1: Apply the setting of 'IO device data exchange management setting area' (Un\G17009 to Un\G17016)
Address b15 b14 b13
Un\G17017 15 14 13

Un\G17024 127 126 125
Each number in the table represents an IO device ID. Each bit corresponds to the IO device ID. For IO device IDs, refer to the
following.
Page 82 [General Configuration] tab
b12 b11 b10 b9 b8
12 11 10 9 8
124 123 122 121 120
b12 b11 b10 b9 b8
12 11 10 9 8
124 123 122 121 120
b7 b6 b5 b4 b3
7 6 5 4 3
119 118 117 116 115
b7 b6 b5 b4 b3
7 6 5 4 3
119 118 117 116 115
Appendix 2 Buffer Memory
b2 b1 b0
2 1 0
114 113 112
A
b2 b1 b0
2 1 0
114 113 112
APPX
145