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Typical Applications; Parallel Connection - Epson S1F76610 series Technical Manual

Cmos dc/dc converter (voltage doubler / tripler) & voltage regulator
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S1F76610 Series

TYPICAL APPLICATIONS

Voltage Tripler with Regulator
The following figure shows the circuit required to triple
the input voltage, regulate the result and add a tempera-
ture gradient of –0.4%/°C. Note that the high input im-
pedance of RV requires appropriate noise countermea-
sures.
V
= 0 V
DD
1
C1 +
10 µF
2
3
5 V
C2
+
10 µF
4
5
6
7
V
= –5 V
I
+
10 µF

Parallel Connection

Connecting two or more chips in parallel reduces the
output impedance by 1/n, where n is the number of de-
vices used.
Only the single output smoothing capacitor, C3, is re-
V
= 0 V
DD
+
C1
10 µF
C2
+
10 µF
5 V
V
= –5 V
I
2–12
14
R
13
R1
RV
R
100 kΩ
OSC
1 MΩ
12
to
R2
1 MΩ
11
10
9
V
REG
8
V
= –15 V
O
C3
1
14
2
13
3
12
4
11
5
10
6
9
7
8
Converting a Voltage Tripler to a Voltage
Doubler
To convert this curcuit to a voltage doubler, remove ca-
pacitor C2 and short circuit CAP2– to V
V
= 0 V
DD
5 V
+
C4
10 µF
= –8 V
V
= –5 V
I
R
RV
=
V
RV
R
1
quired when any number of devices are connected in
parallel. Also, the voltage regulator in one chip is suffi-
cient to regulate the combined output.
1
+
C1
10 µF
2
R
OSC
1 MΩ
3
C2
+
10 µF
4
5
6
7
+
C3
10 µF
EPSON
1
14
C1 +
10µF
2
13
3
12
C2
+
10µF
4
11
5
10
6
9
7
8
+
C3
10 µF
14
13
R
OSC
1 MΩ
12
11
10
9
8
V
= –15 V
O
.
O
R
OSC
1 MΩ
V
= –15 V
O
R
RV
100 kΩ
to
1 MΩ
+
C4
10 µF
V
= –10 V
REG
S1F70000 Series
Technical Manual

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