Viavi T-BERD MTS 5800 Getting Started Manual page 212

Appendix A Specifications
MSAM specifications
DTE emulation
Table 65
tion mode.
Table 65 EIA-530/EIA-530A unbalanced DTE emulation specifications
Specification
User controllable leads
Sync Timing Mode
Rx Timing Sources
Sync Timing Mode
Tx Timing Sources
DCE emulation
Table 66
tion mode.
Table 66 EIA-530/EIA-530A unbalanced DCE emulation specifications
Specification
User controllable leads
Sync Timing Mode
Rx Timing Sources
Sync Timing Mode
Tx Timing Sources
Page 188
lists specifications for EIA-530/EIA-530A unbalanced testing in DTE emula-
lists specifications for unbalanced EIA-530/EIA-530A testing in DCE emula-
T-BERD/MTS/SC Getting Started Guide
22046537, Rev. 016
Description
– RTS
– DTR
– LL
– RL
– Interface (from the RT circuit)
– Interface Recovered
– Interface (from the RT circuit)
– Interface (from the TT circuit)
– Interface Recovered
– Internal Synthesizer
– External Clock
Description
– RLSD
– DSR
– CTS
– TM
– RI (for EIA-530A only)
– Interface (from the TT circuit)
– Internal Synthesizer
– External Clock
– Interface Recovered
– Interface (from the TT circuit)
– Internal Synthesizer
– External Clock
– Interface Recovered
March 2018