Eia-530/Eia-530A Balanced Interface Specifications - Viavi T-BERD MTS 5800 Getting Started Manual

Appendix A Specifications
MSAM specifications
Table 57
Specification
Sync Timing Mode
Rx Timing Sources
Sync Timing Mode
Tx Timing Sources

EIA-530/EIA-530A balanced interface specifications

Recommendation EIA-530/EIA-530A describes a data communications interface that
uses balanced V.11 amplifiers for clock and data circuits, and unbalanced V.10 ampli-
fiers for signaling circuits.
balanced and unbalanced circuits.
Table 58 EIA-530/EIA-530A specifications
Specification
Timing modes
Maximum speed
Minimum output range
V.11
V.10
Maximum input range
V.11
V.10
Rise/Fall times
V.11
V.10
Receiver minimum input sensitivity
V.11
V.10
Hysteresis
Page 184
DCE emulation specifications (Continued)
V.24
Table 58
T-BERD/MTS/SC Getting Started Guide
22046537, Rev. 016
Description
– Interface (from the TT circuit)
– Internal Synthesizer
– External Clock
– Interface Recovered
– Interface (from the TT circuit)
– Internal Synthesizer
– External Clock
– Interface Recovered
lists EIA-530/EIA-530A specifications for both
Description
Synchronous
20 Mbps
+/- 2 V terminated
+/- 4 V unterminated
+/- 10 V
+/- 10 V
10 nS
500 nS
+/- 200 mV
+/- 200 mV
Meets minimum input range
March 2018