New Charge Pump Ics - Sanyo EP92H Brochure

Cell phone devices
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Support for High-Resolution CCDs

New Charge Pump ICs

Features of New Charge Pump ICs
CCD image sensors require a high drive voltage of 10 to 20 V. This 10 to 20 V level is created by stepping up the 3 V
power supply level.
Since conventional charge pump voltage step-up technologies suffer from increased power loss when used to step up
the original voltage by over three times, their use in cell phones was problematic.
SANYO has, however, discovered a way of fusing their high level analog circuit and device technologies to overcome
this problem.
This new charge pump technology can step up a regulated voltage by a factor of three or higher with an efficiency as
high as 70%. Furthermore it can provide an output current of several tens of mA.
SANYO was the first in the industry to develop a high-performance charge pump.
This new charge pump technology can provide both positive and negative stepped up levels, can be combined into
multiple stages, and can provide multiple output levels. Thus this circuit technology is optimal for use in future camera
cell phones that include a megapixel-class CCD image sensor.
High efficiency
(Prior to the regulator: 90 to 95 %)
Coilless, low noise
Supports high output current designs
The only external components are thin form
capacitors (no coils or diodes required)
Can provide both positive and negative
stepped-up outputs
Supports fine step-up step sizes
+0.5 × n × V
DD
-0.5 × n × V
(n: integer)
DD
Optimal for use as the power supply in
portable equipment
Sample characteristics of a high-current
charge pump (single supply voltage
3 )
Plus step-up
Dependency of efficiency on the supply voltage
90
12
80
10
70
60
8
2.9 V
50
3.1 V
6
3.3 V
40
3.5 V
3.7 V
30
4
20
V
=3.3V
DD
2
At I
=50 mA, efficiency=80.6%
OUT
10
At I
=100 mA, efficiency=72.0%
OUT
Maximum efficiency: 80.8%
0
0
0
10
20
30
40
50
60
70
80
90
100
0
Output current, I
(mA)
OUT
28
IPBlock diagram
Clock generator & driver
Clock
C1
C2
Cn
Cn+1
V DD
V IN
V OUT
Charge pump
Output voltages from positive and negative step-up operation
Minus step-up
Positive step-up voltage vs. output current
Negative step-up voltage vs. output current
-12
3.7 V
-10
3.3 V
2.9 V
-8
-6
-4
I
=-50 mA
OUT
-2
At V
=2.9 V, V
=7.78 V
DD
PP
At V
=3.3 V, V
=9.03 V
DD
PP
At V
=3.7 V, V
=10.26 V
DD
PP
-0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
Output current, I
(mA)
Output current, I
OUT
This IC is based on a unique SANYO idea and is a high-efficiency charge pump IC that was newly-developed taking advantage
of CMOS technologies that fuse SANYO's circuit and process technologies. This IC is optimal for power supplies in portable
electronic equipment.
This IC introduces technologies that completely overturn the previous common knowledge that although charge pump circuits
were low noise, they suffered from poor efficiency.
Charge pump power supply application
The ability to provide a stepped-up voltage with low noise makes this circuit optimal for
embedding in modules.
CCD Power Supply IC for Camera Cell Phones
LV5711FN
Regulates a 3.3 to 4.5 V battery level
to 3.1 V and steps up that level 3×
and 6× using a charge pump, to
provide the two regulated power
supply levels required by the CCD
image sensor.
VH = +15.0 V
V
Regulator
O
VL = -8 V
Two independent charge pump
systems are provided for VH and VL
Built-in regulators for the analog
system power supply, vertical driver
system, and DSP core
3.7 V
3.3 V
2.9 V
I
=50 mA
OUT
At V
=2.9 V, V
=-7.44 V
DD
bb
At V
=3.3 V, V
=-8.71 V
DD
bb
At V
=3.7 V, V
=-9.96 V
DD
bb
50
60
70
80
90
100
(mA)
OUT
+15 V(10 mA)
3 V
Charge pump
-8 V(5 mA)
+7 V(500 A)
3 V
Charge pump
-8 V(5 mA)
3V
Charge pump
+4.5 V(100 mA)
Block diagram
3.3 to 4.5 V
1 F
OUT2
7
1 F
VBAT3
10
VBAT4
13
OUT3
11
1 F
VSS2
9
OUT4
1.8 V / 100 mA
12
1 F
FVREF
26
0.1 F
VDD3
17
19
VSS4
15
VSS5
0.47 F
20
C21A
(VDD 1)
18
C21B
0.47 F
21
C22A
(VDD 2)
16
C22B
0.47 F
22
C23A
(VDD 3)
14
C23B
VL_C24
23
(VDD 3)
1 F
VL_C25
24
1 F
STBY
30
1.2-MHz
SLEEP
29
Oscillator
31
EN
Note: Short OUT1 to VDD1 through VDD4.
CCD
LTPS
White LED
Under
development
VBAT2
VBAT1
4
8
VSS1
6
3.1 V / 100 mA
3.1 V / 100 mA
1 F
OUT1
LDO
LDO
5
VDD1,2,3,4
39
VDD1
3.1 V / 1 mA
32
VDD2
40
0.22 F
C11A
LDO
(VDD 1)
38
C11B
41
0.22 F
C12A
(VDD 2)
37
C12B
6 times
42
0.22 F
C13A
step up
Bandgap
circuit
(VDD 3)
36
voltage
C13B
reference
1.19 V
43
0.22 F
C14A
(VDD 4)
-3 times
35
C14B
step up
circuit
44
0.22 F
C15A
(VDD 5)
34
C15B
Timing
33
generator
VSS3
3
VSS6
VH_C16
1
Sequence
(VDD 6)
1 F
-8-V Reg
generator
VH_C17
15-V Reg
2
1 F
1/2 Divider
27
NC
28
25
VDD4
VSS7
* Values in parentheses are actual
applied voltages to the capacitor.
29

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