Philips DVD723/001 Service Manual page 71

Circuit Descriptions, List of Abbreviations, and IC Data
IR Receiver
The IR controller in the slave processor handles both RC5 and
RC6 signals. The logic is +5V for 'high' and 0V for 'low'.
P50 Interface (only for DVD743 models)
P50 (or Easylink) is a bi-directional serial interface for
communication between video equipment. For European sets,
this communication goes via pin 10 of the double SCART.
FTD Display
The slave uP drives the 11-segment FTD. It provides a
negative DC switching drive voltage. As the display consists of
eleven segments, there are eleven grid signals (G1-G11)
controlling each respective grid.
The slave processor has an internal square signal generator
(42 kHz), to generate the AC filament voltage. TS7105/7103
and 7106 amplify the square signal before it is applied to the
display (VAC= VFIL_1 - VFIL_2, VRMS≈ 2.4V). The necessary
power supply of -26V is derived (via zener diode 6101) from the
-32V supply directly from the Switching Mode Power Supply
(SMPS).
Slave Processor Interface
STDBY|ON
FRONT STDBY
* STDBY_CTRL LED
(1 x Tact Switch)
* For DVD743 models
IR
Figure 9-5
The block diagram above, illustrates the interfaces of the slave
uP. The start-up sequence is as follows:
1. The required IC voltage is the +5VSTBY, which is present
during Standby Mode.
2. When the RESET circuit (7108/7102) is triggered by the
+5VSTBY, the slave uP initialises.
3. This will set the STDBY_CTRL signal to LOW, which will
switch on the +3V3 and +5V.
4. Once these voltages are provided, the host uP (on the
SD4.0 mono board) will reset.
5. Now, the host uP will initialise, and indicate the slave uP to
activate the Standby Mode (STBY_CTRL) signal.
6. The player wakes up from the Standby Mode when any
button is pressed on the front panel, or when the 'Power'
button is pressed on the Remote Control.
Note: The slave uP will not reset successfully if the 8MHz clock
oscillator has not stabilised (check on pin 8 of item 7113/7101).
9.5 Audio/Video (A/V) and SCART
The video output from the STi55xx is RGB, YC and CVBS.
These signals enter the A/V Board via connector 1100.
All these analogue video signals, from the SD4.0 Monoboard,
first go through the transistor (item 7168, 7169, 7170, 7160,
7161, 7162, 7163, 7164, 7132) for impedence matching before
going directly to the cinch, SVHS and SCART connector.
However for double scart models, the RGB signals go directly
to the SCART connector 1103.
The '0/6/12' switch signal on pin 8 of the single SCART
connector, depends on the logic state of two other signals:
SCART0 from the µP and STBY_CTRL from the slave µP.
SIO_CLK
STi55xx
A/V BOARD
SIO_DATA
HOST
OTHERS
FRONT CTRL
TMP87CH74
OPEN|CLOSE
slave uP
STOP
(Tact Switch)
PLAY|PAUSE
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This is done according to the following table:
Status Truth Table
SCART_0 STBY_CTRL
0 0
0 1
1 0
1 1
9.5.1 Audio Path
Audio DAC circuitry
LEFT
x 2 x 2
LPF
VFM2002 LEAD
A/V BOARD
The STi55xx supplies I2S data and PCM_CLK master clock to
the new audio DAC (item 7200, AK4382AVT).
The decoded analogue output of both left and right channel is
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balanced. These are filtered (3-pole LPF) and amplified with
OpAmp LM833 (item 7211). The gain of this OpAmp is two
times.
There is only 2X two stereo output from the A/V Board, a
subwoofer, and Digital audio out on coaxial and optical
connector.
The audio DAC accepts only +5V inputs with +3V3 tolerance.
During STDBY mode, there will be no power to the audio DAC.
The registers of the audio DAC are in their default values each
time the power to the IC is cut-off. The slave uP is required to
program the DAC each time after exiting from STDBY mode.
This requires three signal lines.
• CSN - Chip Select Pin.
• CCLK - Control Clk Input Pin.
• CDTI - Control Data Input Pin in Serial Mode.
CCLK and CDTI are connected to P1 and P2 of host uP (via
conn 1104) respectively for communication between the slave
uP and STi55xx.
The host uP (STi55xx) will indicate the slave uP when to
program the audio DAC after waking up from STDBY mode.
The audio MUTE signal depends on the logic state of two other
signals:
• KILL: This signal comes from the host processor (STi55xx)
and is meant to mute the outputs during switch on/off.
• KILL_LR: This is a signal from the audio DAC, when it
receives no input for a certain time (8192 LRCK cycles). It
can be tested in STOP, PAUSE and during track changes.
The logic level for the MUTE signal is -3V < LOW < 0V and 0V
< HIGH < +3V.
DVD 723-743
0|6|12 Function
12V 4:3 aspect ratio DVD
0V TV display
6V 16:9 aspect ratio DVD
0V TV display
Figure 9-6
RIGHT S/W
SCART LEFT
SCART R GHT
x 1
x 1
LPF LPF
LFE_SEL
Control
LPF
Left Channel
CSN
AK4382AVT
CDTI
(Audio DAC)
CCLK
Right Channel
PCM_CLK
I2S Data
Figure 9-7
9. EN 71
STi55xx
SD4.0X
MONOBOARD
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