Z-Axis Amplifier; Intensity Gate; Pulse Circuits - HP 1331A Operating And Service Manual

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(
(
Model 1331A
4-31.
Z-AXIS
AMPLIFIER.
4-32.
The
z-axis amplifier
provides the voltage
and
current gain
required
to
drive
the intensity
gate, per-
mitting
external
intensity
control (z-axis
modulation
).
4-33.
INTENSITY
GATE.
4-34.
Intensity is
controlled
by
three
inputs to the
intensity
gate:
the de output
from
the INTENSITY
control,
the dynamic
output
from
the z-axis amplifier,
and
the
blanking
signal
from the pulse
circuits.
The
three
inputs
are summed
in
the
input
circuit and
drive
the
input to
the gate amplifier.
The
amplitude
of the
blanking
signal
is large enough to
override
the
other inputs.
The
gate amplifier provides
the dyna mic
ra nge
to drive
the
CRT between complete
cutoff and
maximum
brightness.
4-35.
CONTROL
CIRCUITS.
4-36.
The
control circuits
determine mode (WRITE
and
STORE), initiate
the erase cycle (ERASE),
determine
persistence of the display
(PERSISTENCE),
and determine store
time
(store time
adj).
All
these
functions
are controlled
by
front
panel
controls ex-
cept store
time adj, which
is
an
internal adjustment
located
on the program
board, A6.
4-37.
PU LSE
CIRCUITS.
4-38. The pulse
circuits
provide the operating
a
nd
timing signals for the mode and
erase
functions. The
pulse
circuits
are shown
in
greater
detail in
figure
4-5.
The
inputs are
a
nalog
and
digital
commands from
the
control
circuits and the outputs
a
re timed
wave-
forms
a
nd de
voltages
to control the storage and
variable
persistence
elements of the
CRT.
Some of the
tra
nsistor
switches
function
as
logic circuits and
are
shown on
the block diagrams
as
NOR (negated
OR)
gates.
If
any
input to
a
NOR
gate
is
HI, the
output
will be LO;
if all inputs are
LO,
the output
will be
HI. HI
a
nd LO
refer to
logic
states.
HI
is
the
more
positive
of
two different
logic
levels. The
voltages
designa
ted
are
probably different
at
different
points
in
the circuit.
4-39.
Write
Mode.
See
figure
4-5A.
A
write
comm and
(LO) is applied
on
the mode input
to the
inverter.
The HI output
of
the
inverter
causes
LO
outputs from the write gate
a
nd flood
gun gate.
The LO output from the
flood
gun gate
affects
the
flood
gun switch in two ways:
it inhibits
the
input
from the
pulse
generator (no pulses
pass through
the
flood
gun switch)
a
nd
causes
the
output of
the
flood
gun switch
to
go
HI. This turns the
CRT
flood
gun on.
4-40. The
LO
output
from
the write gate activates
the
blan
king
gate. The
HI
output
from
the
blanking
gate
causes
an
unblanking
command (LO)
to be
applied
by
the output
of
the
blanking amplifier to the
gate
a mplifier.
The
LO
output from the
write
gate
also
enables
the storage gate; this
permits the pulses
from the
pulse
generator to
turn the
storage
gate
on
and
off.
The
resultant
pulses are applied
through
the storage erase circuit
to the
CRT storage
mesh.
4-41.
Store
Mode.
See
figure 4-5B.
A
store com-
ma
nd (HI)
is
applied
on the
mode input
to the
in-
verter.
The
LO output
from the inverter
causes a
HI
output from the
write
gate and
flood
gun
gate.
4-42. The HI
output from the
flood gun
gate enables
the
pulse generator
input
to the
flood
gun switch.
The flood gun
switch
a pplies
the amplified
pulses
to
the
CRT flood
gun
accelerator.
4-43.
The HI output from
the
write gate
causes the
output
of the blanking gate to go
LO.
This
causes
the
blanking
amplifier
to
apply
a
blanking command
(HI)
to the gate amplifier.
The LO
output of
the
blanking gate also operates
the deflector
switch,
causing
-49
volts to be
applied
to one
side
of the x-
axis
a mplifier.
This
deflects
a
ny
stray
electrons from
the write gun
away
from
the target area of the CRT.
4-44. The
HI output
of the write gate
causes
the out-
put
of
the
storage
gate to go
LO. In this
condition,
the pulse generator
input
to
the storage gate is
in-
hibited
and
the pulses do not appear at the
output
of the
storage
gate.
The
output
of
the storage
gate
is
clamped in the LO
state
causing the
storage switch
to
apply
+3.5
volts
to the
CRT storage
mesh.
4-46.
Erase
Function. See figure 4-5C. Before
the
erase function
can
be
activated, the
WRITE
push-
button must be pressed. When pressed, the ERASE
pushbutton
applies
+
158
volts to the
erase
switch,
the
storage erase
circuit,
a
nd directly
to the
CRT
storage
mesh
.
4-46. The
time during which the ERASE pushbutton
is manually closed is called prime
time.
There is
no
limit
set for
prime time;
it
depends on
the
operator.
During
prime
time, +
158
volts
is
applied to
the pulse
circuits to accomplish
three
actions.
First,
+ 158
volts
is
applied
directly
to
the
CRT
storage
mesh
(see
fig-
ure
4-3 a
nd
paragraph 4-13). Second,
+158
volts
is
applied
to the
erase
timing
circuit;
this causes a
ca
pacitor to be
charged
in preparation for
the
basic
RC timing action.
Third, +158
volts
is
applied
to
the
storage
erase
circuit;
this causes
a
capacitor
to
be
dis-
charged in preparation
for
another
RC timing action.
Prime time is indicated
in
figure
4-5C
as time period A.
4-47. When
the
ERASE pushbutton
is
released,
the
+
158
volts
is removed
a
nd
the RC
timing actions
be-
gin
.
These timing actions
create
an
erase
timing
period
a
pproximately
800
milliseconds
long. The
erase
timing period
is indicated
in
figure
4-5C as
time period
C.

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