Block Diagram -Dsp Section - Sony HCD-FZ900KW Service Manual

HCD-FZ900KW/FZ900M
5-4. BLOCK DIAGRAM – DSP Section –
J501
IC501
COAXIAL WAVE
SHAPE
X301
TV DIGITAL IN
IC502
24.576MHz
OPTICAL
RECEIVER
OPTICAL 2
L-IN
AUDIO
E
SECTION
R-IN
(Page 25)
ACLK
ALRCK
ABCK
RF
A
AMP_D00
SECTION
AMP_D01
(Page 23)
AMP_D02
FZ900M
LCH
4
RCH
2
SD2
26
SD1
16
BCK1
15
BCK2
24
LRCK1
CN103 14
LRCK2
EZW-T100 23
GND DET
S-AIR 25
TRANSMITTER
ADC_SEL
12
I2C_SDA
19
I2C_SCL
18
RESN RESET
11
GPIO2 INT
7
• SIGNAL PATH
: TUNER
HCD-FZ900KW/FZ900M
IC304
DIR
5 DIN2 (I) AUDIO (O) 24
(COAX)
DATA (O) 16
DIR_ZERO
21 XOUT (O)
DIR_RST
22 XIN (I) XMODE (I) 48
DIR_CLK DIR_CLK
CL (I) 38
DIR_CE
AMP
H
4 DIN (I) CE (I) 37
DIR_DIN DIR_DIN SECTION
(OPT)
DI (I) 36
(Page 27)
DIR_DO
DO (O) 35
DIR_ERR
ERROR (O) 34
CSFLAG
CSFLAG (O) 25
DIR_XSTATE
XSTATE (O) 17
BCK (O) 14
LRCK (O) 15
CKOUT (O) 13
IC306
SACD SELECT
IC303 SACD_SEL
1 A/B
A/D CONVERTER
SCKI 6 4Y 12
13 VINL 14 4A
13 4B
14 VINR LRCK 7 11 3A 3Y 9
10 3B
BCK 8 5 2A 2Y 7
6 2B
DOUT 9 2 1A 1Y 4
3 1B
SI_C
SI_D
DSP_MASTER
DSP_MASTER
AUDIO
G
L-CH
SECTION
R-CH
(Page 25)
SD2
SD1
BCK
I AMP
SECTION
(Page 27)
LRCK
SD2 (SL/SR)
SD1 (DMIX)
BCK
LRCK
IC802
CLOCK GENERATOR
3 2A
X800 IC807
12.288kHz A/D CONVERTER
5 2Y
6 3A 3Y 2 6 SCKI
L-CH
13 VINL DOUT 9
R-CH
14 VINR BCK 8
LRCK 7
IC700
DSP
97 NONAUDIO FLAG2
SI_A
78 DSPIA DAI_P11
Lt/Rt DPSOE DAI_P10 77
FL/FR DPSOA DAI_P6 64
SL/SR DPSOB DAI_P7 65
C/SW DPSOC DAI_P8 70
DPDVBCK DAI_P17 87
DPDVRCK DAI_P16 86
IC706
EEPROM
94 DPFSCK DAI_P20
LRCK
88 DPLRCK DAI_P18
MOSI
127
BCK
89 DPBCK DAI_P19 MISO 126
SI_B
LPCM FL/FR
79
DPSIB DAI_P12
SPICLK 125
LPCM SBL/SBR
82
DPSIE DAI_P15
LPCM SL/SR
80 142
CLKIN
DPSIC DAI_P13
X700
25MHz
LPCM C/SW
81 XTAL 143
DPSID DAI_P14
SPI_MAS DAI_P15 63
SF_CE FLAG3 98
FLAG0 INT_REQ 15
FLAG1 DIR_ERR 16
SPIDS 122
RESET 121
IC805
SAMPLE RATE CONVERTER
9 SDIT SDTO 24
IC808
8 IBICK OBICK 25
DATA SELECT
OLRCK 26
7 ILRCK
18 IMCLK 1 A Y 5
2 B
4 SMUTE
ADC_SEL
3 PDN A/B 6
IC806
SAMPLE RATE CONVERTER
9 SDIT SDTO 24
8 BICK OBICK 25
OLRCK 26
7 ILRCK
18 IMCLK
4 SMUTE
3 PDN
26 26
AMP_DMIX
AMP_D1
AMP_D2
AMP_D3
AMP
J
BCKO
SECTION
(Page 27)
LRCKO
MCKO
IC705
Q700
AND GATE
DELAY
DIR_XSTATE
5
7
6
IC703
DATA LATCH
2
3 1 D Q 4
1
2 CLK
DSP_MISO
SD 2
SI 5
IC702
SCK 6
BUS BUFFER
CE 1
DSP_MOSI
3 5
7
DSP_SPICLK
SPICLK
6 2
1
IC701
DATA SELECT
DSP_SF_CE
1
5
2
6
SF_MASTER DSP_MASTER
SF_CE
DIR_XSTATE
DIR_ERR
DIR_CE
FZ900KW
DIR_DO
SDIN_B (Surr)
CSFLAG
13
DIR_RST
DIR_ZERO
SACD_SEL
SDIN_A (2nd)
20
INT
CN803 RESET
EZW-RT10 DET
ADC_SEL
S-AIR
TRANSCEIVER I2C_SDA
SDIN_C I2C_SCL
19
BCK
17
LRCK
15
I2C_SDA
14
I2C_SCL
11
DET
3
INT
7
RESET
12
VCC_3.3V
2
VCC+3.3V
(S-AIR-INC)
IC503 (4/6)
SYSTEM CONTROL
22 DSP_MISO
DSP_MOSI
24
23 DSP_SPICLK
21 DSP_SF_CE
68 A.CAL_OUT/DSP_INTR
25 DSP_SPIDS
27 DSP_RESET
17 DIR_XSTATE
10 DIR_ERR
70 DIR_HCE/eHDMI_SEL
100 DIR_HDOUT
19 DIR_CSFLAG
11 DIR_RST
18 DIR_ZERO
69 SACD_SEL
33 S-AIR_GPIO2/CLK1
37 S-AIR_RST/C_SW_SEL
34 S-AIR_DET/RST1
38 S-AIR_ADC_SEL/DRIVER_C_EN
30 E2P_SDA/S-AIR_SDA
29 E2P_CLK/S-AIR_CLK
IC505
EEPROM
5 SDA
6 SCL