Intel® Many Integrated Core Architecture Overview - Intel Xeon Phi Developer's Quick Start Manual

Intel® Many Integrated Core Architecture Overview
The Intel® Xeon Phi™ Coprocessor has up to 61 in-order Intel® MIC Architecture processor cores running at
1GHz (up to 1.3GHz). The Intel® MIC Architecture is based on the x86 ISA, extended with 64-bit addressing and
new 512-bit wide SIMD vector instructions and registers. Each core supports 4 hardware threads. In addition
to the cores, there are multiple on-die memory controllers and other components.
Each core includes a newly-designed Vector Processing Unit (VPU). Each vector unit contains 32 512-bit
vector registers. To support the new vector processing model, a new 512-bit SIMD ISA was introduced.
The VPU is a key feature of the Intel® MIC Architecture-based cores. Fully utilizing the vector unit is critical for
best Intel® Xeon Phi™ Coprocessor performance. It is important to note that Intel® MIC Architecture cores do
not support other SIMD ISAs (such as MMX™, Intel® SSE, or Intel® AVX).
Each core has a 32KB L1 data cache, a 32KB L1 instruction cache, and a 512KB L2 cache. The L2 caches of all
cores are interconnected with each other and the memory controllers via a bidirectional ring bus, effectively
creating a shared last-level cache of up to 32MB. The design of each core includes a short in-order pipeline.
There is no latency in executing scalar operations and low latency in executing vector operations. Due to the
short in–order pipeline, the overhead for branch misprediction is low.
For more details on the machine architecture, please refer to the Intel® Xeon Phi™ Coprocessor Software
Developer's Guide posted at
Intel® Xeon Phi™ Coprocessor D
Figure 2: Architecture overview of an Intel® MIC Architecture core
http://software.intel.com/mic-developer
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