Microprocessor Clock Synthesizer; Serial Peripheral Interface (Spi) - Motorola GM-950 Manual

Open Controller
To start SBEP communication this voltage must be above 6V. This condition generates a µP
interrupt via VR0102, Q0105, Q0104, Q0106 and enables the BUS+ line for communication via
Q0122, Q0121.
2.8

Microprocessor Clock Synthesizer

The clock source for the microprocessor system is generated by the ASFIC (U0201). Upon power-
up the synthesizer U5701 (UHF) / U3701 (VHF) / U2701 (MB) generates a 2.1 MHz waveform that is
routed from the RF section (via C0202) to the ASFIC (on U0201-E1) For the main board controller
the ASFIC uses 2.1MHz as a reference input clock signal for its internal synthesizer. The ASFIC, in
addition to audio circuitry, has a programmable synthesizer which can generate a synthesized signal
ranging from 1200Hz to 32.769MHz in 1200 Hz steps.
When power is first applied, the ASFIC will generate its default 3.6864 MHz CMOS square wave µP
CLK (on U0201-D1) and this is routed to the microprocessor (U0101-73). After the microprocessor
starts operation, it reprograms the ASFIC clock synthesizer to a higher µP CLK frequency (usually
7.9488 MHz) and continues operation.
The ASFIC may be reprogrammed to change the clock synthesizer frequencies at various times
depending on the software features that are executing. In addition, the clock frequency of the
synthesizer is changed in small amounts if there is a possibility of harmonics of this clock source
interfering with the desired radio receive frequency.
The ASFIC synthesizer loop uses C0228, C0229 and R0222 to set the switching time and jitter of
the clock output. If the synthesizer cannot generate the required clock frequency it will switch back to
its default 3.6864MHz output.
Because the ASFIC synthesizer and the µP system will not operate without the 2.1MHz reference
clock, it (and the voltage regulators) should be checked first when debugging the system.
2.9

Serial Peripheral Interface (SPI)

The µP communicates to many of the ICs through its SPI port. This port consists of SPI TRANSMIT
DATA (MOSI) (U0101-1), SPI RECEIVE DATA (MISO) (U0101-80), SPI CLK (U0101-2) and chip
select lines going to the various ICs, connected on the SPI PORT (BUS). This BUS is a synchronous
bus, in that the timing clock signal CLK is sent while SPI data (SPI TRANSMIT DATA or SPI
RECEIVE DATA) is sent. Therefore, whenever there is activity on either SPI TRANSMIT DATA or SPI
RECEIVE DATA there should be a uniform signal on CLK. The SPI TRANSMIT DATA is used to send
serial from a µP to a device, and SPI RECEIVE DATA is used to send data from a device to a µP. The
only device from which data can be received via SPI RECEIVE DATA is the EEPROM (U0104 or
U0107) and a control head with graphical display (N4 model).
On the controller there are three ICs on the SPI BUS, ASFIC (U0201-F2), EEPROM (U0104-1 or
U0107-1) and D/A (U0731-6). In the RF sections there is one IC on the SPI BUS which is the
FRAC-N Synthesizer. The SPI TRANSMIT DATA and CLK lines going to the RF section are filtered
by L0131/L0132 to minimize noise. The chip select lines for the IC´s are decoded by the address
decoder U0105.
The SPI BUS is also used for the control head. U0106-2,3 buffer the SPI TRANSMIT DATA and CLK
lines to the control head. U0106-1 switch off the CLK signal for the LCD display if it is not selected
via LCD CE and Q0141.
5C.3-4 Theory of Operation