Circuitdescription - Yaesu FT-2500M Technical Supplement

Circuit
Description
tuned to
its
peak level, preset
by
Center-Stop
trimmer
VR2007.
Transmit Signal Path
Speech
input from
the microphone is deliv-
ered via the
Mic
(]ack) Unit and DISPLAY Unit to
the CNTL Unit, where
it
passed through Mic
Mute switch
D2003 (DAP202K) for amplification
and pre-emphasis
by
Q2007-1 (NJM2902M-1/4).
To
prevent over-deviation, the audio
is processed
by IDC
(instantaneous deviation control)
stage
Q2007-2/a,
and then lowpass filtered by
Q2007-3/t
&.
-41+(N,naz9o2M)
before
delivery to
the modula-
tor on
the VCO Unit.
If
a
CTCSS
tone is enabled
for
transmission,
the subaudible tone from
microprocessor
Q2006
on the CNTL Unit
is lowpass
filtered by
Q2001,-t
and mixed with
the IDC-processed speech audio.
Also, DTMF tones
generated
by
the
FRC-6 op-
tion(if installed)
or
directly from the microproces-
soq,
are
applied to
the
transmit audio chain
at
the
input
of the IDC
stage. The microprocessor also
disables
microphone
at
Mic Mute switch
D2003.
The modulating audio is delivered to
diode
D305 (1SV214) on the
VCO
Unit,
frequency
modulating the PLL carrier up to + 5 kHz from
the
unmodulated carrier at the transmitting fre-
quency.
The modulated signal from
transmitter
VCO Q303
(2SC3356)
is
buffered
by
Q305
(2SC2759) and delivered to the Main Unit for
amplification
by
Q1.01.2
(2SC2759), Q1011
(MMBR951L) and Q1010 (2SC20s3). The low
level transmit signal is then finally
amplified by
PA module Q1009 (M67781L)
up to
50 watts.
Harmonic spurious radiation
in
the
final output
is
suppressed
by
a 3-pole lowpass
filter on
the
Main Unit, and the transmit signal then
passes
through
1/+-w av
e
antenna switch
D1
0
1
6
( U
M 94
1
5)
before delivery to the antenna.
Automatic Tiansmit
Power Control
RF
power output from the final amplifier
is
sampled
by
CL064
and rectified
by
DL01.7
(1SS97). The resulting
DC is
passedbyhigh/me-
dium/low
power controller Q1017 (FMS1) and
transmit
inhibit gate Q1018 (lMX1) to
Automatic
Power Controller Q1019 (2581143S) which
regulates supply voltage
to
transmitter
RF
ampli-
fiers
Q1009
and
Q1010, so as
to maintain
stable
high, medium or.low output power under vary-
ing antenna loading conditions.
Spurious Suppression
Generation of spurious products by
the trans-
mitter is minimized by the fundamental carrier
frequency being equal to the final transmitting
frequency, modulated directly
in
the transmit
VCO.
Additional harmonic
suppression is pro-
vided
by
a 3-pole lowpass
filter
consisting of
LL002, LL013,
LL01,4
and
C1002, CL061,
C1.063,
C1065-C1067, and C1I64,
resulting in
more than
50 dB harmonic suppression
(for
transmitting
frequencies
in
the amateur band) prior to deliv-
ery to the antenna.
PLL
Erequency Synthesizer
PLL circuitry on the Main Unit
consists of
prescaler Q1025 (MC12O22SLAD) and PLL sub-
system IC Q1024 (MC1451 s9F2),which contains
a
reference oscillator / divider,
serial-to-parallel
data latch, programmable
divider and a
phase
comparator. Stability is obtained
by
a
regulated
5-V supply
to
Q1024
and temperature compen-
sating capacitors
associated
with
L2.8-MHz fre-
quency reference crystal
X1002.
Receiver
VCO Q301 (2SC3356)
on the VCO
Unit
oscillates between
118.6
and
152.6
according
to
the
programmed receiving frequency.
The
VCO
ouput
is buffered
by
Q305 (2SC2759) on
the VCO Unit, and then retumed to
the
MAIN
Unit
where
a
sample of the output
is
buffered by
Q1028 (2S,C2714Y) for application to prescaler/-
swallow counter
Q1025. There
the VCO signal is
divided by
64
or
65,
according to
a
control signal
from the data latch section
of
Q1024,before
being
applied to the programmable divider
section
of
the PLL chip.
The data latch section of
Q1024 also receives
serial
dividing
data
from
microprocessor Q2006
on the CNTL Unit, which
causes
the
predivided
VCO signal to be further divided
by
23,720
-
30,520
in
the programmable
divider
section, de-
pending upon the desired receive frequency,
so
as
to produce
a S-kHz
or
6.25-kHz
derivative of
the current VCO frequency. Meanwhile,
the refer-
ence
divider
section
of
Q1024
divides the
12.8-
MHz crystal
reference
by
2560
(or
2048) to
produce the S-kHz (or 6.25-kHz) loop
reference
(respectively).
The
5-kHz (or
6.25-kHz) signal
from the pro-
grammable
divider (derived from
the VCO) and
that derived from the crystal
are
applied to
the
1-8
FT-2500M
Technical Supplement