GE VersaMax PLC User Manual page 137

Input/ Output
address
enable
R
DIR
STEP
ST
ok
Instruction Set Reference
For public disclosure
10.1.12.2 Parameters for the Bit Sequencer Function
Choices
R
flow
flow
flow
I, Q, M, T, G, R, AI, AQ,
constant, none
I, Q, M, T, SA, SB, SC, G,
R, AI, AQ, none
flow, none
10.1.12.3 Example
In the example, the Bit Sequencer operates on register memory %R0001. Its static data is
stored in registers %R0010–12. When CLEAR is active, the sequencer is reset and the
current step is set to step number 3. The first 8 bits of %R0001 are set to zero.
When NXT_SEQ is active and CLEAR is not active, the bit for step number 3 is cleared
and the bit for step number 2 or 4 (depending on whether DIR is energized) is set.
NXT_CYC
CLEAR
DIRECT
CONST
00003
%R0001
Description
Address is the location of the bit sequencer's
current step, length, and the last enable and OK
status.
When the function is enabled, if it was not
enabled on the previous sweep and if R is not
energized, the bit sequence shift is performed.
When R is energized, the bit sequencer's step
number is set to the value in STEP (default = 1),
and the bit sequencer is filled with zeros, except
for the current step number bit.
When DIR is energized, the bit sequencer's step
number is incremented prior to the shift.
Otherwise, it is decremented.
When R is energized, the step number is set to
this value.
ST contains the first word of the bit sequencer.
Optional.
The OK output is energized whenever the
function is enabled.
BIT_
SEQ
R
DIR
STEP
ST
%R0010
GFK-1503E User Manual 137