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Block Diagrams
Port
No.
41
DB6
42
DB5
43
DB4
44
DB3
45
DB2
46
DB1
47
C1F1
48
C1F2
49
C2F1
50
C2F2
51
C2FL
52
/PBCK
53
DVSS2
54
FSDW
55
ULKFS
56
/JIT
57
C4M
58
C16M
59
/WE
60
/CS
61
XTALSEL
62
TEST0
63
CDROM
64
SRAM
65
TEST1
66
EFMI
67
ADATAI
68
/ISTAT
69
TRCNT
70
LOCK
71
PBFR
72
SMEF
73
SMON
74
DVDD2
75
SMDP
76
SMSD
77
BCKI
78
TESTV
79
DSPEED
80
LRCHI
9-14
Port
I/O
SARM data I/O port 6
I/O
SARM data I/O port 5
I/O
SARM data I/O port 4
I/O
SARM data I/O port 3
I/O
SARM data I/O port 2
I/O
SARM data I/O port 1 (LSB)
I/O
Monitoring output for C1 error correctiong (RA1)
I/O
Monitoring output for C1 error correctiong (RA2)
I/O
Monitoring output for C2 error correctiong (RA3)
I/O
Monitoring output for C21 error correctiong (RA4)
I/O
C2 decoder flag (RA5, "H" : When the processing C2 code is impossible
correction status.)
I/O
Output of VCO/2 (4.3218MHz) (RA6)
I/O
Digital ground2
I/O
Window or unprotected frame sync (RA7)
I/O
Frame sync protection state (RA8)
I/O
Display of either RAM overflow or underflow for ±4 frame jitter margin
(RA9)
I/O
Only monitoring signal (4.2336MHz) (RA10)
I/O
16.9344MHz signal output (RA11)
I/O
Terminal for test
I/O
Terminal for test
I
Mode Selection1 (H: 33.8688MHz, L:16.9344MHz)
I
TEST input terminal (GND connection)
I
Mode Selection2 (H: CD-ROM, L: CDP)
I
TEST input terminal (GND connection)
I
TEST input terminal (GND connection)
I
EFM signal input
I
Serial audio data input of 48 bit/Slot (MSB first)
O
The internal status output
I
Tracking counter input signal
O
Output signal of LKFS condition sampled PBFR/16 (if LKFS is "H", LOCK
is "H", if LKFS is sampled "L" at least 8 times by PBFR/16, LOCK is "L")
O
Write frame clock (Lock: 7.35KHz)
O
LPF time constant control of the spindle srvo error signal
O
ON/OFF control signal for spindle servo
-
Digital VDD2
O
Spindle Motor drive (Rough control in the SPEED mode, Phase control
in the PHASE mode)
O
Spindle Motor drive (Velocity control in the PHASE mode)
I
Audio data bit clock input of 48 bit/Slot (2.1168MHz)
I
TEST input terminal (GND connection)
I
TEST input terminal (VDD connection)
I
Channel clock input of 48 bit/Slot (44.1KHz)
Description
Samsung Electronics
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