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Details Of Buffer Memory Addresses - Mitsubishi Electric MELSEC iQ-F FX55-ASL-M User Manual

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Do not write data to "System area".
Doing so may cause malfunction of the programmable controller system.

Details of buffer memory addresses

Input information area
This buffer memory area automatically stores the on/off status of the input signal of the slave module.
■Input information area (Un\G0 to Un\G15)
Address
b15
b14
Un\G0
15
14
Un\G1
31
30
Un\G2
47
46
Un\G3
63
62
Un\G4
79
78
Un\G5
95
94
Un\G6
111
110
Un\G7
127
126
Un\G8
143
142
Un\G9
159
158
Un\G10
175
174
Un\G11
191
190
Un\G12
207
206
Un\G13
223
222
Un\G14
239
238
Un\G15
255
254
Ex.
If a 2-point input slave module (address 10) is connected, the 2 bits from Un\G0.A are occupied for the input signal because
the setting address is 10. (b10 and b11 of Un\G0 turn on or off.)
Data access command
Various data access commands from the CPU module to the FX5-ASL-M are stored as shown below.
■Data access command (Un\G27)
Address
b15
b14
Un\G27
Refer to the following table.
Bit No.
Description
Un\G27 b0
Error flag clear command
Un\G27 b1
Automatic address detection command
Un\G27 b2
Overlap address inspection command
Un\G27 b3 to 7
System area
Un\G27 b8
Parameter access request command for the slave module
Un\G27 b9
Parameter batch read command for the slave module
Un\G27 b10
Parameter batch write command for the slave module
Un\G27 b11 to 15
System area
b13
b12
b11
b10
b9
13
12
11
10
9
29
28
27
26
25
45
44
43
42
41
61
60
59
58
57
77
76
75
74
73
93
92
91
90
89
109
108
107
106
105
125
124
123
122
121
141
140
139
138
137
157
156
155
154
153
173
172
171
170
169
189
188
187
186
185
205
204
203
202
201
221
220
219
218
217
237
236
235
234
233
253
252
251
250
249
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
8
7
6
5
4
24
23
22
21
20
40
39
38
37
36
56
55
54
53
52
72
71
70
69
68
88
87
86
85
84
104
103
102
101
100
120
119
118
117
116
136
135
134
133
132
152
151
150
149
148
168
167
166
165
164
184
183
182
181
180
200
199
198
197
196
216
215
214
213
212
232
231
230
229
228
248
247
246
245
244
b8
b7
b6
b5
b4
Bit status
ON
Execution
Execution
Execution
Execution
Execution
Execution
b3
b2
b1
b0
3
2
1
0
19
18
17
16
35
34
33
32
51
50
49
48
67
66
65
64
83
82
81
80
99
98
97
96
115
114
113
112
131
130
129
128
147
146
145
144
163
162
161
160
179
178
177
176
195
194
193
192
211
210
209
208
227
226
225
224
243
242
241
240
b3
b2
b1
b0
OFF
Standby
Standby
Standby
Standby
Standby
Standby
APPX
Appendix 4 Buffer Memory
A
75

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