D.1.1 Interoperability Document - GE C70 Instruction Manual

APPENDIX D
APPENDIX D IEC 60870-5-104 COMMUNICATIONSD.1OVERVIEW
This document is adapted from the IEC 60870-5-104 standard. For this section the boxes indicate the following:  – used
in standard direction;  – not used;  – cannot be selected in IEC 60870-5-104 standard.
1. SYSTEM OR DEVICE:
 System Definition
 Controlling Station Definition (Master)
 Controlled Station Definition (Slave)
2. NETWORK CONFIGURATION:
 Point-to-Point
 Multiple Point-to-Point
3. PHYSICAL LAYER
Transmission Speed (control direction):
Unbalanced Interchange
Circuit V.24/V.28 Standard:

100 bits/sec.

200 bits/sec.
 300 bits/sec.
 600 bits/sec.

1200 bits/sec.
Transmission Speed (monitor direction):
Unbalanced Interchange
Circuit V.24/V.28 Standard:
 100 bits/sec.

200 bits/sec.

300 bits/sec.

600 bits/sec.
 1200 bits/sec.
4. LINK LAYER
Link Transmission Procedure:

Balanced Transmission

Unbalanced Transmission
Frame Length (maximum length, number of octets): Not selectable in companion IEC 60870-5-104 standard
GE Multilin
 Multipoint
 Multipoint Star
Unbalanced Interchange
Circuit V.24/V.28 Recommended
if >1200 bits/s:

2400 bits/sec.

4800 bits/sec.
 9600 bits/sec.
Unbalanced Interchange
Circuit V.24/V.28 Recommended
if >1200 bits/s:
 2400 bits/sec.

4800 bits/sec.

9600 bits/sec.
Address Field of the Link:

Not Present (Balanced Transmission Only)

One Octet
 Two Octets

Structured

Unstructured
C70 Capacitor Bank Protection and Control System
D.1 OVERVIEW

D.1.1 INTEROPERABILITY DOCUMENT

Balanced Interchange Circuit
X.24/X.27:

2400 bits/sec.

4800 bits/sec.
 9600 bits/sec.
 19200 bits/sec.

38400 bits/sec.

56000 bits/sec.
 64000 bits/sec.
Balanced Interchange Circuit
X.24/X.27:
 2400 bits/sec.

4800 bits/sec.

9600 bits/sec.

19200 bits/sec.
 38400 bits/sec.

56000 bits/sec.

64000 bits/sec.
D
D-1