Table of Contents
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68
WBLSH
69
ATFG
70
WBLCLK
71
RFPDSH
72
WFPDSH
206
WRSTOP
Miscellaneous Interface (4)
169
TEST_MODE
170
PRST
74
XTALO
75
XTALI
Host Interface (31)
122
HRST#
142,140,138,
HD15 ~ HD0
135,132,130,
127,124,123,
125,128,131,
133,136,139,
141
144
DMARQ
145
DIOW#
46
3.3V LVTTL output,
Sample pulse for wobble signal.
2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR
Digital wobble signal (22.05 ± 1 K Hz) input
3.3V LV TTL Input,
SMT
3.3V LVTTL output,
Wobble processing clock (432.18K Hz) output for MT1516.
Slew rate,
4mA driving
3.3V LVTTL output,
Sample pulse control signal for RF read APC.
2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR
3.3V LV TTL output,
Sample pulse control signal for RF write APC.
Slew rate,
2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR
3.3V LV TTL Input,
Write procedure stop control input.
SMT, 75K pull-down
3.3V LV TTL input,
Test mode, active high
75K pull-down
3.3V LV TTL Input,
Power on reset input, high active.
SMT
Output
X`tal output.
Input
X`tal input. The working frequency is 33.8688 MHz.
3.3V LV TTL Input,
Host reset input. The active-low input is referred to as hardware
SMT, 75K pull-up
reset and is used to reset this chip.
3.3V LVTTL I/O,
Host Data bus. This is the 8-bit or 16-bit bi-directional data bus
Slew rate, SMT,
to the host. The lower 8 bits, HD0–HD7, are used for 8-bit data
4mA, 6mA, 8mA,
transfers. Normally, data transfers are 16-bit wide.
12mA PDR,
Note :
40K(15K) PPU, 40K
pull-up or pull-down with 40K resistant.(HD6~HD0 is 15K)
(15K)PPD
3.3V LV TTL output,
DMA request. This signal is used for DMA data transfers
12mA driving
between host and device and it shall be asserted by the MT1518
when it is ready to transfer data to or from the host. The
direction of data transfer is controlled by DIOR# and DIOW#.
3.3V LV TTL Input,
Device I/O write. Stop ultra DMA burst.
SMT, 40K pull-up
For Device I/O Write, this signal is the strobe signal asserted by
the host to write device register or the data port.
For Stop Ultra DMA, this signal shall be negated by the host
before data is transferred in an Ultra DMA burst and is asserted
by host during an Ultra DMA burst to signal the termination of
Ultra DMA burst.
All pins except HD7 (no any pull) may be selectively
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