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CQ-C5401H
Pin
Port
Descriptions
I/O
(V)
No.
58
REST
Mechanics deck REST SW input
I
3.3
SW
59
DATA M
AUDIO serial data output
O
1.6
C
60
SO
Serial data output
O
1.2
61
-
-
-
-
62
-
-
-
-
63
/NMI
-
-
3.3
64
/INT0
-
-
3.3
65
/INT1
-
-
3.3
66
BLKCK
Subcode block clock pulse input
I
0
67
/INT3
-
-
3.3
68
CV DD4
CORE CPU system (1.6V) power
-
1.6
supply
69
SW1
Mechanics deck SW1 input
I
0
70
CVSS7
GND
-
0
71
MCLK
Clock output (To Servo DSP)
O
3.3
72
DVSS4
GND
-
0
73
MLD
Command load signal output (To
I
3.3
Servo DSP)
74
MDATA
Command data output (To Servo
O
3.3
DSP)
75
DVDD4
I/O system (3.3V) power supply
-
3.3
76
DVSS5
GND
-
0
77
CLK MD1 Clock mode setting (L fixation)
I
0
78
CLK MD2 Clock mode setting (H fixation)
I
3.3
79
CLK MD3 Clock mode setting (L fixation)
I
-
80
-
-
-
-
81
SW2
Mechanics deck SW2 input
I
0
82
-
-
-
-
83
EMU0
-
-
0
84
EMU/OF
-
-
3.3
F
85
TDO
-
-
3.3
86
TDI
-
-
0
87
/TRST
-
-
3.3
88
TCK
-
-
0
89
TMS
-
-
3.3
90
CVSS8
GND
-
3.3
91
CVDD5
CORE CPU system (1.6V) power
-
0
supply
92
HPIENA
GND
I
1.6
93
DVSS6
GND
-
0
94
-
-
-
-
95
CLKENA Oscillation output Cainabl signal
O
3.3
96
X1
Crystal Connection
O
0
97
X2/CLKIN Crystal Connection
I
0
98
RS
Reset signal input
I
1
99
D0
Data base of FLASH ROM
I/O
3.4
100 D1
I/O
0
101 D2
I/O
0
102 D3
I/O
0
103 D4
I/O
0
104 D5
I/O
0
105 A16
Address bus of FLASH ROM
O
0
106 DVSS7
GND
-
0
107 A17
Address bus of FLASH ROM
O
3.3
108 A18
Address bus of FLASH ROM
O
0
109 A19
Address bus of FLASH ROM
O
0
110 A20
Address bus of FLASH ROM
O
0
111 CVSS9
GND
-
0
112 DVDD5
I/O system (3.3V) power supply
-
3.3
113 D6
Data bus of FLASH ROM
I/O
0
114 D7
I/O
0
115 D8
I/O
0
116 D9
I/O
0
117 D10
I/O
0
Pin
Port
Descriptions
I/O
(V)
No.
118 D11
Data bus of FLASH ROM
I/O
0
119 D12
I/O
0
120 STAT
Status signal input
I
0.4
121 D13
Data path of FLASH ROM
I/O
0
122 D14
I/O
0
123 D15
I/O
0
124
-
-
-
-
125 CVDD6
CORE CPU system (1.6V) power
-
1.6
supply
126 CVSS10 GND
-
0
127
-
-
-
-
128 DVSS8
I/O system (3.3V) power supply
-
0
129
-
-
-
-
130 DVDD6
I/O system (3.3V) power supply
-
3.3
131 A0
Address bus of FLASH ROM
O
0
132 A1
O
0
133 A2
O
3.3
134 A3
O
3.3
135 /RST
Reset signal output (To Servo DSP)
O
3.3
136 A4
Address bus of FLASH ROM
O
3.3
137 A5
O
0
138 A6
O
3.3
139 A7
O
3.3
140 A8
O
0
141 A9
O
3.3
142 CVDD7
CORE CPU system (1.6V) power
-
1.6
supply
143
-
-
-
-
144 DVSS9
GND
-
0
Page 10
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