Page 1 GE Energy Connections Grid Solutions MiCOM P40 Agile P54A, P54B, P54C, P54E Technical Manual Single Breaker Multi-End Current Differential IED (Non Distance) Hardware Version: M,P Software Version: 01 Publication Reference: P54xMED-TM-EN-1...
Page 3: Table Of Contents
Contents Chapter 1 Introduction Chapter Overview Foreword Target Audience Typographical Conventions Nomenclature Compliance Product Scope Ordering Options Features and Functions Current Differential Protection Functions Protection Functions Control Functions Measurement Functions Communication Functions Logic Diagrams Functional Overview Chapter 2 Safety Information Chapter Overview Health and Safety Symbols...
Page 4 Contents P54A/B/C/E 4.1.3 Front Serial Port (SK1) 4.1.4 Front Parallel Port (SK2) 4.1.5 Fixed Function LEDs 4.1.6 Function Keys 4.1.7 Programable LEDs Rear Panel Boards and Modules PCBs Subassemblies Main Processor Board Power Supply Board 6.4.1 Watchdog 6.4.2 Rear Serial Port Input Module - 1 Transformer Board 6.5.1 Input Module Circuit Description...
Page 5 P54A/B/C/E Contents Chapter Overview Settings Application Software Using the HMI Panel Navigating the HMI Panel Getting Started Default Display Default Display Navigation Password Entry Processing Alarms and Records Menu Structure Changing the Settings Direct Access (The Hotkey menu) 3.9.1 Setting Group Selection Using Hotkeys 3.9.2 Control Inputs 3.9.3...
Page 6 Contents P54A/B/C/E Configuring the Protection Communications Setting Up the Phase Differential Characteristic Sensitivity Under Heavy Loads Permissive Intertripping CT Ratio Correction Setting Guidelines 9.10 Feeders with Small Tapped Loads Chapter 7 Autoreclose Chapter Overview Introduction to Autoreclose Autoreclose Implementation Autoreclose Logic Inputs from External Sources 3.1.1 Circuit Breaker Healthy Input 3.1.2...
Page 7 P54A/B/C/E Contents 5.10.1 Single-Phase Autoreclose Cycle Selection Logic Diagram 5.10.2 3-phase Autoreclose Cycle Selection 5.11 Dead Time Control 5.11.1 Dead Time Start Enable Logic Diagram 5.11.2 1-phase Dead Time Logic Diagram 5.11.3 3-phase Dead Time Logic Diagram 5.12 Circuit Breaker Autoclose 5.12.1 Circuit Breaker Autoclose Logic Diagram 5.13...
Page 8 Contents P54A/B/C/E Chapter 9 Current Protection Functions Chapter Overview Phase Fault Overcurrent Protection POC Implementation Directional Element POC Logic Negative Sequence Overcurrent Protection Negative Sequence Overcurrent Protection Implementation Directional Element NPSOC Logic Application Notes 3.4.1 Setting Guidelines (Current Threshold) 3.4.2 Setting Guidelines (Time Delay) 3.4.3 Setting Guidelines (Directional element)
Page 9 P54A/B/C/E Contents Overvoltage Protection Implementation Overvoltage Protection Logic Application Notes 3.3.1 Overvoltage Setting Guidelines Compensated Overvoltage Residual Overvoltage Protection Residual Overvoltage Protection Implementation Residual Overvoltage Logic Application Notes 5.3.1 Calculation for Solidly Earthed Systems 5.3.2 Calculation for Impedance Earthed Systems 5.3.3 Setting Guidelines Chapter 11...
Page 10 Contents P54A/B/C/E 5.8.1 Setting the Thresholds for the Total Broken Current 5.8.2 Setting the thresholds for the Number of Operations 5.8.3 Setting the thresholds for the Operating Time 5.8.4 Setting the Thresholds for Excesssive Fault Frequency CB State Monitoring CB State Monitor Logic diagram Circuit Breaker Control CB Control using the IED Menu CB Control using the Hotkeys...
Page 11 P54A/B/C/E Contents 5.1.1 Resistor Values 5.1.2 PSL for TCS Scheme 1 Trip Circuit Supervision Scheme 2 5.2.1 Resistor Values 5.2.2 PSL for TCS Scheme 2 Trip Circuit Supervision Scheme 3 5.3.1 Resistor Values 5.3.2 PSL for TCS Scheme 3 Chapter 14 Digital I/O and PSL Configuration Chapter Overview Configuring Digital Inputs and Outputs...
Page 12 Contents P54A/B/C/E Long Distance Application Notes Chapter 17 Communications Chapter Overview Communication Interfaces Serial Communication EIA(RS)232 Bus EIA(RS)485 Bus 3.2.1 EIA(RS)485 Biasing Requirements K-Bus Standard Ethernet Communication Hot-Standby Ethernet Failover Redundant Ethernet Communication Supported Protocols Parallel Redundancy Protocol High-Availability Seamless Redundancy (HSR) 5.3.1 HSR Multicast Topology 5.3.2...
Page 13 P54A/B/C/E Contents 5.10.8 Ports On/Off 5.10.9 VLAN 5.10.10 End of Session Simple Network Management Protocol (SNMP) SNMP Management Information Bases Main Processor MIBS Structure Redundant Ethernet Board MIB Structure Accessing the MIB Main Processor SNMP Configuration Data Protocols Courier 7.1.1 Physical Connection and Link Layer 7.1.2 Courier Database...
Page 14 Contents P54A/B/C/E Read-Only DDB Signals Time Synchronisation Demodulated IRIG-B 9.1.1 IRIG-B Implementation SNTP 9.2.1 Loss of SNTP Server Signal Alarm IEEE 1588 Precision time Protocol 9.3.1 Accuracy and Delay Calculation 9.3.2 PTP Domains Time Synchronsiation using the Communication Protocols Chapter 18 Cyber-Security Overview The Need for Cyber-Security...
Page 15 P54A/B/C/E Contents Earth Connnection Current Transformers Voltage Transformer Connections Watchdog Connections EIA(RS)485 and K-Bus Connections IRIG-B Connection Opto-input Connections 4.10 Output Relay Connections 4.11 Ethernet Metallic Connections 4.12 Ethernet Fibre Connections 4.13 RS232 connection 4.14 Download/Monitor Port 4.15 GPS Fibre Connection 4.16 Fibre Communication Connections Case Dimensions...
Page 16 Contents P54A/B/C/E 5.2.6 Test Trip LED 5.2.7 Test User-programmable LEDs 5.2.8 Test Opto-inputs 5.2.9 Test Output Relays 5.2.10 Test Serial Communication Port RP1 5.2.11 Test Serial Communication Port RP2 5.2.12 Test Ethernet Communication Secondary Injection Tests 5.3.1 Test Current Inputs 5.3.2 Test Voltage Inputs Electrical Intermicom Communication Loopback...
Page 17 P54A/B/C/E Contents 15.3 Measure Capacitive Charging Current 15.4 Check Differential Current 15.5 Check Current Transformer Polarity 15.6 On-load Directional Test Final Checks Chapter 21 Maintenance and Troubleshooting Chapter Overview Maintenance Maintenance Checks 2.1.1 Alarms 2.1.2 Opto-isolators 2.1.3 Output Relays 2.1.4 Measurement Accuracy Replacing the Device Repairing the Device...
Page 18 Contents P54A/B/C/E Rear Serial Port 1 Fibre Rear Serial Port 1 Rear Serial Port 2 Optional Rear Serial Port (SK5) IRIG-B (Demodulated) IRIG-B (Modulated) Rear Ethernet Port Copper 2.10 Rear Ethernet Port Fibre 2.10.1 100 Base FX Receiver Characteristics 2.10.2 100 Base FX Transmitter Characteristics 2.11 1 PPS Port...
Page 19 P54A/B/C/E Contents Transit Packaging Performance Type Tests Insulation Creepage Distances and Clearances High Voltage (Dielectric) Withstand Impulse Voltage Withstand Test Environmental Conditions 10.1 Ambient Temperature Range 10.2 Temperature Endurance Test 10.3 Ambient Humidity Range 10.4 Corrosive Environments Electromagnetic Compatibility 11.1 1 MHz Burst High Frequency Disturbance Test 11.2 Damped Oscillatory Test...
Page 20 Contents P54A/B/C/E xviii P54xMED-TM-EN-1...
Page 21 Table of Figures Figure 1: Key to logic diagrams Figure 2: Functional Overview Figure 3: Hardware architecture Figure 4: Coprocessor hardware architecture Figure 5: Exploded view of IED Figure 6: Front panel (60TE) Figure 7: Rear view of populated case Figure 8: Terminal block types Figure 9:...
Page 22 Table of Figures P54A/B/C/E Figure 39: Original current waveforms Figure 40: Ipos and Ineg current waveforms Figure 41: Internal external fault binary Figure 42: CT Compensation Figure 43: Permissive Intertripping example Figure 44: Stub Bus protection Figure 45: Six terminal, four junction topology and ring structure Figure 46: Six terminal ring structure with channel allocation Figure 47:...
Page 23 P54A/B/C/E Table of Figures Figure 79: Successful Autoreclose Signals logic diagram (Module 36) Figure 80: Autoreclose Reset Successful Indication logic diagram (Module 37) Figure 81: Circuit Breaker Healthy and System Check Timers Healthy logic diagram (Module 39) Figure 82: Autoreclose Shot Counters logic diagram (Module 41) Figure 83: CB Control logic diagram (Module 43) Figure 84:...
Page 24 Table of Figures P54A/B/C/E Figure 119: Overfrequency logic (single stage) Figure 120: Rate of change of frequency logic (single stage) Figure 121: Fault recorder stop conditions Figure 122: Broken Current Accumulator logic diagram Figure 123: CB Trip Counter logic diagram Figure 124: Operating Time Accumulator Figure 125:...
Page 25 P54A/B/C/E Table of Figures Figure 159: Five terminal scheme Figure 160: Six terminal scheme Figure 161: IM64 channel fail and scheme fail logic Figure 162: IM64 general alarm signals logic Figure 163: IM64 communications mode and IEEE C37.94 alarm signals Figure 164: IM64 two-terminal scheme extended supervision Figure 165:...
Page 26 Table of Figures P54A/B/C/E Figure 198: 80TE case dimensions Figure 199: RP1 physical connection Figure 200: Remote communication using K-bus Figure 201: InterMicom loopback testing Figure 202: Simulated input behaviour Figure 203: Test example 1 Figure 204: Test example 2 Figure 205: Test example 3 Figure 206:...
Page 27: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION...
Page 28: Circuit Breaker Fail Logic - Part
Chapter 1 - Introduction P54A/B/C/E P54xMED-TM-EN-1...
Page 29: Chapter Overview
P54A/B/C/E Chapter 1 - Introduction CHAPTER OVERVIEW This chapter provides some general information about the technical manual and an introduction to the device(s) described in this technical manual. This chapter contains the following sections: Chapter Overview Foreword Product Scope Features and Functions Logic Diagrams Functional Overview P54xMED-TM-EN-1...
Page 30: Foreword
Chapter 1 - Introduction P54A/B/C/E FOREWORD This technical manual provides a functional and technical description of General Electric's P54A, P54B, P54C, P54E, as well as a comprehensive set of instructions for using the device. The level at which this manual is written assumes that you are already familiar with protection engineering and have experience in this discipline.
Page 31: Nomenclature
P54A/B/C/E Chapter 1 - Introduction NOMENCLATURE Due to the technical nature of this manual, many special terms, abbreviations and acronyms are used throughout the manual. Some of these terms are well-known industry-specific terms while others may be special product- specific terms used by General Electric. The first instance of any acronym or term used in a particular chapter is explained.
Page 32: Product Scope
Chapter 1 - Introduction P54A/B/C/E PRODUCT SCOPE The P54A, P54B, P54C and P54E IEDs provide high-speed, multi-ended differential protection (without the need of GPS synchronisation) for electrical feeders having between 2 and 6 terminals, for both overhead line and cable applications.
Page 33: Features And Functions
P54A/B/C/E Chapter 1 - Introduction FEATURES AND FUNCTIONS CURRENT DIFFERENTIAL PROTECTION FUNCTIONS Feature IEC 61850 ANSI Phase segregated current differential protection DifPDIF1 Between 2 and 6 terminal lines/cables Self-synchronization feature InterMiCOM teleprotection for direct device-to-device communication (optional) PROTECTION FUNCTIONS Feature IEC 61850 ANSI Tripping Mode (1 &...
Page 34: Measurement Functions
Chapter 1 - Introduction P54A/B/C/E Feature IEC 61850 ANSI Programmable LEDs LedGGIO Programmable hotkeys Programmable allocation of digital inputs and outputs Fully customizable menu texts Circuit breaker control, status & condition monitoring XCBR CT supervision VT supervision Trip circuit and coil supervision Control inputs PloGGIO1 Power-up diagnostics and continuous self-monitoring...
Page 35: Logic Diagrams
P54A/B/C/E Chapter 1 - Introduction LOGIC DIAGRAMS This technical manual contains many logic diagrams, which should help to explain the functionality of the device. Although this manual has been designed to be as specific as possible to the chosen product, it may contain diagrams, which have elements applicable to other products.
Page 36: Figure 1: Key To Logic Diagrams
Chapter 1 - Introduction P54A/B/C/E Key: Energising Quantity AND gate & Internal Signal OR gate DDB Signal XOR gate Internal function NOT gate Setting cell Logic 0 Setting value Timer Hardcoded setting Pulse / Latch Measurement Cell SR Latch Internal Calculation SR Latch Reset Dominant Derived setting...
Page 37: Functional Overview
P54A/B/C/E Chapter 1 - Introduction FUNCTIONAL OVERVIEW This diagram is applicable to several multi-end current differential protection products in the P40L family; P54A, P54B, P54C and P54E. Use the diagram key to determine the features relevant to the product described in this technical manual.
Page 38 Chapter 1 - Introduction P54A/B/C/E P54xMED-TM-EN-1...
Page 39: Chapter 2 Safety Information
CHAPTER 2 SAFETY INFORMATION...
Page 40 Chapter 2 - Safety Information P54A/B/C/E P54xMED-TM-EN-1...
Page 41: Chapter Overview
P54A/B/C/E Chapter 2 - Safety Information CHAPTER OVERVIEW This chapter provides information about the safe handling of the equipment. The equipment must be properly installed and handled in order to maintain it in a safe condition and to keep personnel safe at all times. You must be familiar with information contained in this chapter before unpacking, installing, commissioning, or servicing the equipment.
Page 42: Health And Safety
Chapter 2 - Safety Information P54A/B/C/E HEALTH AND SAFETY Personnel associated with the equipment must be familiar with the contents of this Safety Information. When electrical equipment is in operation, dangerous voltages are present in certain parts of the equipment. Improper use of the equipment and failure to observe warning notices will endanger personnel.
Page 43: Symbols
P54A/B/C/E Chapter 2 - Safety Information SYMBOLS Throughout this manual you will come across the following symbols. You will also see these symbols on parts of the equipment. Caution: Refer to equipment documentation. Failure to do so could result in damage to the equipment Warning: Risk of electric shock...
Page 44: Installation, Commissioning And Servicing
Chapter 2 - Safety Information P54A/B/C/E INSTALLATION, COMMISSIONING AND SERVICING LIFTING HAZARDS Many injuries are caused by: Lifting heavy objects ● Lifting things incorrectly ● ● Pushing or pulling heavy objects Using the same muscles repetitively ● Plan carefully, identify any possible hazards and determine how best to move the product. Look at other ways of moving the load to avoid manual handling.
Page 45: Ul/Csa/Cul Requirements
P54A/B/C/E Chapter 2 - Safety Information Caution: NEVER look into optical fibres or optical output connections. Always use optical power meters to determine operation or signal level. Warning: Testing may leave capacitors charged to dangerous voltage levels. Discharge capacitors by rediucing test voltages to zero before disconnecting test leads. Caution: Operate the equipment within the specified electrical and environmental limits.
Page 46: Equipment Connections
Chapter 2 - Safety Information P54A/B/C/E Caution: Digital input circuits should be protected by a high rupture capacity NIT or TIA fuse with maximum rating of 16 A. for safety reasons, current transformer circuits must never be fused. Other circuits should be appropriately fused to protect the wire used. Caution: CTs must NOT be fused since open circuiting them may produce lethal hazardous voltages...
Page 47: Pre-Energisation Checklist
P54A/B/C/E Chapter 2 - Safety Information Caution: Use a locknut or similar mechanism to ensure the integrity of stud-connected PCTs. Caution: The recommended minimum PCT wire size is 2.5 mm² for countries whose mains supply is 230 V (e.g. Europe) and 3.3 mm² for countries whose mains supply is 110 V (e.g. North America).
Page 48: Upgrading/Servicing
Chapter 2 - Safety Information P54A/B/C/E Note: For most Alstom equipment with ring-terminal connections, the threaded terminal block for current transformer termination is automatically shorted if the module is removed. Therefore external shorting of the CTs may not be required. Check the equipment documentation and wiring diagrams first to see if this applies.
Page 49: Decommissioning And Disposal
P54A/B/C/E Chapter 2 - Safety Information DECOMMISSIONING AND DISPOSAL Caution: Before decommissioning, completely isolate the equipment power supplies (both poles of any dc supply). The auxiliary supply input may have capacitors in parallel, which may still be charged. To avoid electric shock, discharge the capacitors using the external terminals before decommissioning.
Page 50: Regulatory Compliance
Chapter 2 - Safety Information P54A/B/C/E REGULATORY COMPLIANCE Compliance with the European Commission Directive on EMC and LVD is demonstrated using a technical file. EMC COMPLIANCE: 2014/30/EU The product specific Declaration of Conformity (DoC) lists the relevant harmonised standard(s) or conformit assessment used to demonstrate compliance with the EMC directive.
Page 51 P54A/B/C/E Chapter 2 - Safety Information Where: 'II' Equipment Group: Industrial. '(2)G' High protection equipment category, for control of equipment in gas atmospheres in Zone 1 and 2. This equipment (with parentheses marking around the zone number) is not itself suitable for operation within a potentially explosive atmosphere.
Page 52 Chapter 2 - Safety Information P54A/B/C/E P54xMED-TM-EN-1...
Page 53: Chapter 3 Hardware Design
CHAPTER 3 HARDWARE DESIGN...
Page 54 Chapter 3 - Hardware Design P54A/B/C/E P54xMED-TM-EN-1...
Page 55: Chapter Overview
P54A/B/C/E Chapter 3 - Hardware Design CHAPTER OVERVIEW This chapter provides information about the product's hardware design. This chapter contains the following sections: Chapter Overview Hardware Architecture Mechanical Implementation Front Panel Rear Panel Boards and Modules P54xMED-TM-EN-1...
Page 56: Hardware Architecture
Chapter 3 - Hardware Design P54A/B/C/E HARDWARE ARCHITECTURE The main components comprising devices based on the Px4x platform are as follows: The housing, consisting of a front panel and connections at the rear ● The Main processor module consisting of the main CPU (Central Processing Unit), memory and an interface ●...
Page 57: Figure 4: Coprocessor Hardware Architecture
P54A/B/C/E Chapter 3 - Hardware Design FPGA Comms between main and coprocessor board SRAM Ch1 for current differential input Comms interface Ch2 for current differential input Coprocessor board V00291 Figure 4: Coprocessor hardware architecture P54xMED-TM-EN-1...
Page 58: Mechanical Implementation
Chapter 3 - Hardware Design P54A/B/C/E MECHANICAL IMPLEMENTATION All products based on the Px4x platform have common hardware architecture. The hardware is modular and consists of the following main parts: Case and terminal blocks ● Boards and modules ● Front panel ●...
Page 59: List Of Boards
P54A/B/C/E Chapter 3 - Hardware Design Case width (TE) Case width (mm) Case width (inches) 40TE 203.2 60TE 304.8 80TE 406.4 Note: Not all case sizes are available for all models. LIST OF BOARDS The product's hardware consists of several modules drawn from a standard range. The exact specification and number of hardware modules depends on the model number and variant.
Page 60 Chapter 3 - Hardware Design P54A/B/C/E Coprocessor board with fibre connections for current differential inputs + GPS Coprocessor board with dual fibre inputs + GPS input. P54xMED-TM-EN-1...
Page 61: Front Panel
P54A/B/C/E Chapter 3 - Hardware Design FRONT PANEL FRONT PANEL Depending on the exact model and chosen options, the product will be housed in either a 40TE, 60TE or 80TE case. By way of example, the following diagram shows the front panel of a typical 60TE unit. The front panels of the products based on 40TE and 80TE cases have a lot of commonality and differ only in the number of hotkeys and user-programmable LEDs.
Page 62: Keypad
Chapter 3 - Hardware Design P54A/B/C/E The bottom compartment contains: A compartment for a 1/2 AA size backup battery (used to back up the real time clock and event, fault, and ● disturbance records). A 9-pin female D-type front port for an EIA(RS)232 serial connection to a PC. ●...
Page 63: Front Parallel Port (Sk2)
P54A/B/C/E Chapter 3 - Hardware Design Note: The front serial port does not support automatic extraction of event and disturbance records, although this data can be accessed manually. 4.1.3.1 FRONT SERIAL PORT (SK1) CONNECTIONS The port pin-out follows the standard for Data Communication Equipment (DCE) device with the following pin connections on a 9-pin connector.
Page 64: Programable Leds
Chapter 3 - Hardware Design P54A/B/C/E 4.1.7 PROGRAMABLE LEDS The device has a number of programmable LEDs, which can be associated with PSL-generated signals. The programmable LEDs for most models are tri-colour and can be set to RED, YELLOW or GREEN. However the programmable LEDs for some models are single-colour (red) only.
Page 65: Rear Panel
P54A/B/C/E Chapter 3 - Hardware Design REAR PANEL The MiCOM Px40 series uses a modular construction. Most of the internal workings are on boards and modules which fit into slots. Some of the boards plug into terminal blocks, which are bolted onto the rear of the unit. However, some boards such as the communications boards have their own connectors.
Page 66: Figure 8: Terminal Block Types
Chapter 3 - Hardware Design P54A/B/C/E Figure 8: Terminal block types Note: Not all products use all types of terminal blocks. The product described in this manual may use one or more of the above types. P54xMED-TM-EN-1...
Page 67: Boards And Modules
P54A/B/C/E Chapter 3 - Hardware Design BOARDS AND MODULES Each product comprises a selection of PCBs (Printed Circuit Boards) and subassemblies, depending on the chosen configuration. PCBS A PCB typically consists of the components, a front connector for connecting into the main system parallel bus via a ribbon cable, and an interface to the rear.
Page 68: Main Processor Board
Chapter 3 - Hardware Design P54A/B/C/E The products in the Px40 series typically contain two sub-assemblies: The power supply assembly comprising: ● ○ A power supply board An output relay board ○ The input module comprising: ● One or more transformer boards, which contains the voltage and current transformers (partially or ○...
Page 69: Power Supply Board
P54A/B/C/E Chapter 3 - Hardware Design POWER SUPPLY BOARD Figure 11: Power supply board The power supply board provides power to the unit. One of three different configurations of the power supply board can be fitted to the unit. This is specified at the time of order and depends on the magnitude of the supply voltage that will be connected to it.
Page 70: Figure 12: Power Supply Assembly
Chapter 3 - Hardware Design P54A/B/C/E Figure 12: Power supply assembly The power supply outputs are used to provide isolated power supply rails to the various modules within the unit. Three voltage levels are used by the unit’s modules: 5.1 V for all of the digital circuits ●...
Page 71: Watchdog
P54A/B/C/E Chapter 3 - Hardware Design Figure 13: Power supply terminals 6.4.1 WATCHDOG The Watchdog contacts are also hosted on the power supply board. The Watchdog facility provides two output relay contacts, one normally open and one normally closed. These are used to indicate the health of the device and are driven by the main processor board, which continually monitors the hardware and software when the device is in service.
Page 72: Rear Serial Port
Chapter 3 - Hardware Design P54A/B/C/E Figure 14: Watchdog contact terminals 6.4.2 REAR SERIAL PORT The rear serial port (RP1) is housed on the power supply board. This is a three-terminal EIA(RS)485 serial communications port and is intended for use with a permanently wired connection to a remote control centre for SCADA communication.
Page 73: Input Module - 1 Transformer Board
P54A/B/C/E Chapter 3 - Hardware Design Figure 15: Rear serial port terminals An additional serial port with D-type presentation is available as an optional board, if required. INPUT MODULE - 1 TRANSFORMER BOARD Figure 16: Input module - 1 transformer board The input module consists of the main input board coupled together with an instrument transformer board.
Page 74: Input Module Circuit Description
Chapter 3 - Hardware Design P54A/B/C/E 6.5.1 INPUT MODULE CIRCUIT DESCRIPTION 8 digital inputs Optical Optical Isolator Isolator Noise Noise filter filter Parallel Bus Buffer Transformer board Serial Link Serial A/D Converter interface V00239 Figure 17: Input module schematic A/D Conversion The differential analogue inputs from the CT and VT transformers are presented to the main input board as shown.
Page 75: Transformer Board
P54A/B/C/E Chapter 3 - Hardware Design The opto-isolated logic inputs can be configured for the nominal battery voltage of the circuit for which they are a part, allowing different voltages for different circuits such as signalling and tripping. Note: The opto-input circuitry can be provided without the A/D circuitry as a separate board, which can provide supplementary opto-inputs.
Page 76: Input Board
Chapter 3 - Hardware Design P54A/B/C/E 6.5.3 INPUT BOARD Figure 19: Input board The input board is used to convert the analogue signals delivered by the current and voltage transformers into digital quantities used by the IED. This input board also has on-board opto-input circuitry, providing eight optically- isolated digital inputs and associated noise filtering and buffering.
Page 77: Standard Output Relay Board
P54A/B/C/E Chapter 3 - Hardware Design Terminal Number Opto-input Terminal 17 Common Terminal 18 Common STANDARD OUTPUT RELAY BOARD Figure 20: Standard output relay board - 8 contacts This output relay board has 8 relays with 6 Normally Open contacts and 2 Changeover contacts. The output relay board is provided together with the power supply board as a complete assembly, or independently for the purposes of relay output expansion.
Page 78: Irig-B Board
Chapter 3 - Hardware Design P54A/B/C/E Terminal Number Output Relay Terminal 11 Relay 6 NO Terminal 12 Relay 6 NO Terminal 13 Relay 7 changeover Terminal 14 Relay 7 changeover Terminal 15 Relay 7 common Terminal 16 Relay 8 changeover Terminal 17 Relay 8 changeover Terminal 18...
Page 79: Fibre Optic Board
P54A/B/C/E Chapter 3 - Hardware Design FIBRE OPTIC BOARD Figure 22: Fibre optic board This board provides an interface for communicating with a master station. This communication link can use all compatible protocols (Courier, IEC 60870-5-103, MODBUS and DNP 3.0). It is a fibre-optic alternative to the metallic RS485 port presented on the power supply terminal block.
Page 80: Rear Communication Board
Chapter 3 - Hardware Design P54A/B/C/E REAR COMMUNICATION BOARD Figure 23: Rear communication board The optional communications board containing the secondary communication ports provide two serial interfaces presented on 9 pin D-type connectors. These interfaces are known as SK4 and SK5. Both connectors are female connectors, but are configured as DTE ports.
Page 81 P54A/B/C/E Chapter 3 - Hardware Design This is a communications board that provides a standard 100-Base Ethernet interface. This board supports one electrical copper connection and one fibre-pair connection. There are several variants for this board as follows: 100 Mbps Ethernet board ●...
Page 82: Redundant Ethernet Board
Chapter 3 - Hardware Design P54A/B/C/E 6.11 REDUNDANT ETHERNET BOARD IRIG-B Link Fail Pin3 connector Pin 2 Pin 1 Link channel B Link channel A (green LED) (green LED) Activity channel Activity channel B A (yellow LED) (yellow LED) V01009 Figure 25: Redundant Ethernet board This board provides dual redundant Ethernet (supported by two fibre pairs) together with an IRIG-B interface for timing.
Page 83 P54A/B/C/E Chapter 3 - Hardware Design Link Fail Connector (Ethernet Board Watchdog Relay) Closed Open Link fail Channel 1 (A) Link ok Channel 1 (A) Link fail Channel 2 (B) Link ok Channel 2 (B) LEDs Function Flashing Green Link Link ok Link broken Yellow...
Page 84: Coprocessor Board
Chapter 3 - Hardware Design P54A/B/C/E 6.12 COPROCESSOR BOARD Figure 26: Fully populated Coprocessor board Note: The above figure shows a coprocessor complete with GPS input and 2 fibre-optic serial data interfaces, and is not necessarily representative of the product and model described in this manual. These interfaces will not be present on boards that do not require them.
Page 85 P54A/B/C/E Chapter 3 - Hardware Design If, for example, Device A is transmitting to Device B information about the value of its measured current, the information Device A is receiving from Device B about the current measured at the same time, may reach device B at a different time.
Page 86 Chapter 3 - Hardware Design P54A/B/C/E P54xMED-TM-EN-1...
Page 87: Chapter 4 Software Design
CHAPTER 4 SOFTWARE DESIGN...
Page 88 Chapter 4 - Software Design P54A/B/C/E P54xMED-TM-EN-1...
Page 89: Chapter Overview
P54A/B/C/E Chapter 4 - Software Design CHAPTER OVERVIEW This chapter describes the software design of the IED. This chapter contains the following sections: Chapter Overview Sofware Design Overview System Level Software Platform Software Protection and Control Functions P54xMED-TM-EN-1...
Page 90: Sofware Design Overview
Chapter 4 - Software Design P54A/B/C/E SOFWARE DESIGN OVERVIEW The device software can be conceptually categorized into several elements as follows: The system level software ● The platform software ● ● The protection and control software These elements are not distinguishable to the user, and the distinction is made purely for the purposes of explanation.
Page 91: System Level Software
P54A/B/C/E Chapter 4 - Software Design SYSTEM LEVEL SOFTWARE REAL TIME OPERATING SYSTEM The real-time operating system is used to schedule the processing of the various tasks. This ensures that they are processed in the time available and in the desired order of priority. The operating system also plays a part in controlling the communication between the software tasks, through the use of operating system messages.
Page 92: System Level Software Initialisation
Chapter 4 - Software Design P54A/B/C/E 3.4.2 SYSTEM LEVEL SOFTWARE INITIALISATION The initialization process initializes the processor registers and interrupts, starts the watchdog timers (used by the hardware to determine whether the software is still running), starts the real-time operating system and creates and starts the supervisor task.
Page 93 P54A/B/C/E Chapter 4 - Software Design If the problem is with the battery status or the IRIG-B board, the device continues in operation. For problems detected in any other area, the device initiates a shutdown and re-boot, resulting in a period of up to 10 seconds when the functionality is unavailable.
Page 94: Platform Software
Chapter 4 - Software Design P54A/B/C/E PLATFORM SOFTWARE The platform software has three main functions: To control the logging of records generated by the protection software, including alarms, events, faults, and ● maintenance records To store and maintain a database of all of the settings in non-volatile memory ●...
Page 95: Protection And Control Functions
P54A/B/C/E Chapter 4 - Software Design PROTECTION AND CONTROL FUNCTIONS The protection and control software processes all of the protection elements and measurement functions. To achieve this it has to communicate with the system services software, the platform software as well as organise its own operations.
Page 96: Fourier Signal Processing
Chapter 4 - Software Design P54A/B/C/E board and converts these to 8 samples per cycle based on the nominal frequency. The coprocessor calculates the Fourier transform of the fixed rate samples after every sample, using a one-cycle window. This generates current measurements eight times per cycle which are used for the differential protection algorithm.
Page 97: Programmable Scheme Logic
P54A/B/C/E Chapter 4 - Software Design Ideal anti-alias filter response Fourier Response Real anti-alias filter without anti-alias filter response Fourier Response with anti-alias filter 2 3... Alias frequency 50 Hz 1200 Hz 2400 Hz V00306 Figure 28: Frequency Response (indicative only) PROGRAMMABLE SCHEME LOGIC The purpose of the programmable scheme logic (PSL) is to allow you to configure your own protection schemes to suit your particular application.
Page 98: Disturbance Recorder
Chapter 4 - Software Design P54A/B/C/E may be triggered by a fatal error in the relay in which case it may not be possible to successfully store a maintenance record, depending on the nature of the problem. For more information, see the Monitoring and Control chapter. DISTURBANCE RECORDER The disturbance recorder operates as a separate task from the protection and control task.
Page 99: Chapter 5 Configuration
CHAPTER 5 CONFIGURATION...
Page 100 Chapter 5 - Configuration P54A/B/C/E P54xMED-TM-EN-1...
Page 101: Chapter Overview
P54A/B/C/E Chapter 5 - Configuration CHAPTER OVERVIEW Each product has different configuration parameters according to the functions it has been designed to perform. There is, however, a common methodology used across the entire product series to set these parameters. Some of the communications setup can only be carried out using the HMI, and cannot be carried out using settings applications software.
Page 102: Settings Application Software
Chapter 5 - Configuration P54A/B/C/E SETTINGS APPLICATION SOFTWARE To configure this device you will need to use the Settings Application Software. The settings application software used in this range of IEDs is called MiCOM S1 Agile. It is a collection of software tools, which is used for setting up and managing the IEDs.
Page 103: Using The Hmi Panel
P54A/B/C/E Chapter 5 - Configuration USING THE HMI PANEL Using the HMI, you can: Display and modify settings ● View the digital I/O signal status ● ● Display measurements Display fault records ● Reset fault and alarm indications ● The keypad provides full access to the device functionality using a range of menu options. The information is displayed on the LCD.
Page 104: Navigating The Hmi Panel
Chapter 5 - Configuration P54A/B/C/E Note: As the LCD display has a resolution of 16 characters by 3 lines, some of the information is in a condensed mnemonic form. NAVIGATING THE HMI PANEL The cursor keys are used to navigate the menus. These keys have an auto-repeat function if held down continuously.
Page 105: Default Display
P54A/B/C/E Chapter 5 - Configuration If there are alarms present, the yellow Alarms LED will be flashing and the menu display will read as follows: Alarms / Faults Present HOTKEY Even though the device itself should be in full working order when you first start it, an alarm could still be present, for example, if there is no network connection for a device fitted with a network card.
Page 106: Default Display Navigation
Chapter 5 - Configuration P54A/B/C/E Plant reference (user-defined) For example: Plant Reference MiCOM HOTKEY Access Level For example: Access Level HOTKEY In addition to the above, there are also displays for the system voltages, currents, power and frequency etc., depending on the device model. DEFAULT DISPLAY NAVIGATION The following diagram is an example of the default display navigation.
Page 107: Password Entry
P54A/B/C/E Chapter 5 - Configuration If the device is cyber-secure but is not yet configured for NERC compliance (see Cyber-security chapter), a warning will appear when moving from the "NERC compliant" banner. The warning message is as follows: DISPLAY NOT NERC COMPLIANT.
Page 108: Menu Structure
Chapter 5 - Configuration P54A/B/C/E Press Clear To Reset Alarms To clear all alarm messages, press the Clear key. To return to the display showing alarms or faults present, and leave the alarms uncleared, press the Read key. Depending on the password configuration settings, you may need to enter a password before the alarm messages can be cleared.
Page 109: Changing The Settings
P54A/B/C/E Chapter 5 - Configuration Setting Column Description Sys Fn Links (Row 03) Third setting within first column … … … VIEW RECORDS Second Column definition Select Event [0...n] First setting within second column Menu Cell Ref Second setting within second column Time &...
Page 110: Direct Access (The Hotkey Menu)
Chapter 5 - Configuration P54A/B/C/E Note: For the protection group and disturbance recorder settings, if the menu time-out occurs before the changes have been confirmed, the setting values are discarded. Control and support settings, howeverr, are updated immediately after they are entered, without the Update settings? prompt.
Page 111: Circuit Breaker Control
P54A/B/C/E Chapter 5 - Configuration To access the hotkey menu from the default display, you press the key directly below the HOTKEY text on the LCD. The following screen will appear. ¬User32 STG GP® HOTKEY MENU EXIT Press the right cursor key twice to get to the first control input, or the left cursor key to get to the last control input. ¬STP GP User02®...
Page 112 Chapter 5 - Configuration P54A/B/C/E The first cell down in the FUNCTION KEYS column is the Fn Key Status cell. This contains a binary string, which represents the function key commands. Their status can be read from this binary string. FUNCTION KEYS Fn Key Status 0000000000...
Page 113: Line Parameters
P54A/B/C/E Chapter 5 - Configuration LINE PARAMETERS This product requires information about the circuit to which it is applied. This includes line impedance, residual compensation, and phase rotation sequence. For this reason circuit parameter information must be input using the LINE PARAMETERS settings. These LINE PARAMETERS settings are used by protection elements as well as by the fault locator.
Page 114: Residual Compensation
Chapter 5 - Configuration P54A/B/C/E RESIDUAL COMPENSATION To improve accuracy of impedance measuring elements such as those used in distance protection and fault locators, the total loop impedance calculation Z can be calibrated by the positive sequence impedance between the relaying point and the fault (Z ) using the following equation: ⋅...
Page 115 P54A/B/C/E Chapter 5 - Configuration is the residual current of the parallel line (measured) ● ● is the residual compensation coefficient is the mutual compensation coefficient ● In the above equation: − where: is the total zero sequence impedance of the line (a complex value) ●...
Page 116: Date And Time Configuration
Chapter 5 - Configuration P54A/B/C/E DATE AND TIME CONFIGURATION The date and time setting will normally be updated automatically by the chosen UTC (Universal Time Co- ordination) time synchronisation mechanism when the device is in service. You can also set the date and time manually using the Date/Time cell in the DATE AND TIME column.
Page 117: Without A Timing Source Signal
P54A/B/C/E Chapter 5 - Configuration Ensure that the IED is receiving valid time synchronisation messages by checking that the PTP Status cell reads Valid Master. Check that Act. Time Source cell reads PTP. This indicates that the IED is using PTP as the source for its time.
Page 118: Daylight Saving Time Compensation
Chapter 5 - Configuration P54A/B/C/E DAYLIGHT SAVING TIME COMPENSATION It is possible to compensate for Daylight Saving time using the following settings DST Enable ● ● DST Offset DST Start ● ● DST Start Day DST Start Month ● DST Start Mins ●...
Page 119: Settings Group Selection
P54A/B/C/E Chapter 5 - Configuration SETTINGS GROUP SELECTION You can select the setting group using opto inputs, a menu selection, and for some models the hotkey menu or function keys. You choose which method using the Setting Group setting in the CONFIGURATION column. There are two possibilities;...
Page 120 Chapter 5 - Configuration P54A/B/C/E P54xMED-TM-EN-1...
Page 121: Chapter 6 Current Differential Protection
CHAPTER 6 CURRENT DIFFERENTIAL PROTECTION...
Page 122 Chapter 6 - Current Differential Protection P54A/B/C/E P54xMED-TM-EN-1...
Page 123: Chapter Overview
P54A/B/C/E Chapter 6 - Current Differential Protection CHAPTER OVERVIEW This product provides biased, phase-segregated, numerical Current Differential protection. This chapter introduces the principles and theory behind Current Differential protection and describes how they are implemented in this product. Guidance for applying this protection is also provided. The current differential protection is enabled by default, but it can be disabled if you don’t want to use it.
Page 124: Current Differential Protection Principle
Chapter 6 - Current Differential Protection P54A/B/C/E CURRENT DIFFERENTIAL PROTECTION PRINCIPLE Current differential protection is based on Kirchoff’s Law. It generally uses the Merz-Price principle in which the sum of the currents entering the protected zone should equal the sum of the currents leaving the protected zone. A difference between these currents is known as differential current.
Page 125: Multi-Ended Line Differential Protection
P54A/B/C/E Chapter 6 - Current Differential Protection MULTI-ENDED LINE DIFFERENTIAL PROTECTION Current differential protection has been used for many years to protect the transmission lines and distribution feeders. Previous protection relays could protect 2 or 3 ended schemes, but these products introduce multi-ended differential protection, which can protect lines or cables up to maximum of six terminals with sub-cycle for up to 4- ended schemes, and 1.25 cycle for 5 or 6 ended schemes.
Page 126: Differential Characteristics
Chapter 6 - Current Differential Protection P54A/B/C/E In- zone E00761 Figure 32: Sample multi-ended system The algorithm uses the following differential current and bias current: Differential current is the RMS value of the current that is sum of the currents at all ends. For example, in ●...
Page 127: Figure 33: Current Differential Discriminative Criterion
P54A/B/C/E Chapter 6 - Current Differential Protection Where I and K are setting values: : The minimum threshold for differential current; : The slope changing point (when the bias current is larger than this value, security is much more important than reliability for differential protection);...
Page 128: Basic Algorithm
Chapter 6 - Current Differential Protection P54A/B/C/E 2.3.3 BASIC ALGORITHM The multi-ended differential sample based algorithm employs the RMS value, in which the instantaneous differential current is the sum of instantaneous current of all terminals: ∑ diff Where, i is the current of mth terminal; M is the number of terminals; i is instantaneous differential current;...
Page 129: Communication Requirements
Communication connection ports: Ring topology ● Communication protocol: IEEE 37.94 * ● ● Bandwidth: 12*64 kbps Details of communication configuration are described in the Fibre Teleprotection chapter. *A GE recommended third party protocol converter could be used for other protocols such as X21. P54xMED-TM-EN-1...
Page 130: Charging Current Compensation
Chapter 6 - Current Differential Protection P54A/B/C/E CHARGING CURRENT COMPENSATION For both overhead transmission lines and underground cables, there are significant capacitive currents from ground to the conductor due to the equivalent shunt admittance between the line and the ground. If this current is not compensated, the differential current will possibly be higher than the Ibias when there is no fault or even when external fault occurs.
Page 131 P54A/B/C/E Chapter 6 - Current Differential Protection phase ) / ( π is the propagation time delay of traveling waves from one terminal to another; − phase ) / ( π is the gain factor made by propagation attenuation; − P54xMED-TM-EN-1...
Page 132: Synchronisation Of Current Signals
“ping-pong”. Note: GE Multi-ended line differential relays support only ping-pong synchronisation. TIME ALIGNMENT USING PING-PONG TECHNIQUE The following figure demonstrates the ping-pong technique for a two-terminal protection scheme. the two terminals are referred to as “End A”...
Page 133: Remote Terminal Time Alignment
P54A/B/C/E Chapter 6 - Current Differential Protection The device at End A samples its current signals at times tA1, tA2, etc. The device at End B samples its current signals at time tB1, tB2, etc. The sampling of the signals at the two ends are not synchronised, but both operate in the same way.
Page 134: Time Delay Interpolation
Chapter 6 - Current Differential Protection P54A/B/C/E Data from Remote Terminal 3 Data from Remote Terminal 2 Data from Remote Terminal 1 Data from Local Terminal Time E00765 Figure 37: Snapshot of available data for processing at each terminal From the above figure, it is clear that if we take a snapshot of available data for processing from all the terminals, the local terminal has the most recent data.
Page 135: Ct Saturation
CT is severely saturated. The technique is GE patented technique, which is achieved by the correlation of the local measured phase current with the remote current from all ends. Therefore, it eliminates the requirement to detect CT saturation to inhibit protection and it can simply discriminate between internal and external fault.
Page 136: Figure 39: Original Current Waveforms
Chapter 6 - Current Differential Protection P54A/B/C/E Discriminative criteria We define the R as the ratio of ||I || to ||I ( ) || ( ) || − The discriminative criteria is presented below: Rset > Where, Rset is the internal preset value. The CT saturation is determined on a per phase basis.
Page 137: Figure 40: Ipos And Ineg Current Waveforms
P54A/B/C/E Chapter 6 - Current Differential Protection E00771 Figure 40: Ipos and Ineg current waveforms Based on the Rct ratio and discriminative criteria explained above, the example below shows the relay initially detecting an external fault before switching to internal fault at the 0.7 seconds. E00772 Figure 41: Internal external fault binary P54xMED-TM-EN-1...
Page 138: Ct Compensation
Chapter 6 - Current Differential Protection P54A/B/C/E CT COMPENSATION The primary and secondary ratios for the phase current transformers are set in the CT AND VT RATIOS column. These settings are used to display the phase current quantities in the MEASUREMENTS 1 column. The device can be set to display the input current either in primary values or in secondary values.
Page 139: Current Differential Intertripping
P54A/B/C/E Chapter 6 - Current Differential Protection CURRENT DIFFERENTIAL INTERTRIPPING Eight freely assignable intertripping signals are provided by a facility called InterMICOM64, which is described in the chapter on Fibre Teleprotection. In addition there are two intertripping functions associated directly with the Current Differential protection.
Page 140: Stub Bus Differential Protection
Chapter 6 - Current Differential Protection P54A/B/C/E STUB BUS DIFFERENTIAL PROTECTION This product can provide stub-bus protection associated with the differential protection. If you wish to use this feature you must ensure that the current differential protection is enabled. You will need to map one of the opto-isolated inputs to the DDB Stub Bus Enabled using the programmable scheme logic and you will need to enable the feature by setting Ph Diff Stub Bus in the CURRENT DIFF column to Enabled.
Page 141: Application Notes
P54A/B/C/E Chapter 6 - Current Differential Protection APPLICATION NOTES MULTI-END CURRENT DIFFERENTIAL PROTECTION P54A, P54B, P54C and P54E products provide current differential protection for electrical feeders having between 2 and 6 terminals. It is implemented using distributed protection devices located at each feeder terminal with all devices interconnected by a fiber optic communications ring structure.
Page 142: Feeder Topology
Chapter 6 - Current Differential Protection P54A/B/C/E FEEDER TOPOLOGY A single-line diagram is used to describe the feeder topology. The diagram below identifies terminals and Junctions. A terminal (T) represents an external connection point to the protected feeder. A junction (J) represents a connection point, which is internal to the protection scheme.
Page 143: Line Parameter Data
P54A/B/C/E Chapter 6 - Current Differential Protection In the example used, each junction is connected to one or two terminals. A '1' is inserted wherever a junction is connected to a terminal. For example, J1 is connected to both T1 and T2. J2 is connected only to T3. J3 is connected only to T4.
Page 144: Configuring The Protection Communications
Chapter 6 - Current Differential Protection P54A/B/C/E Z0Local Zero Sequence impedance amplitude of the local section length Z0LocalAngle Zero Sequence impedance angle of the local section length Y1Local Positive sequence admittance amplitude of the local section length (the conductance is neglected) Y0Local Zero sequence admittance amplitude of the local section length (the conductance is neglected)
Page 145: Setting Up The Phase Differential Characteristic
P54A/B/C/E Chapter 6 - Current Differential Protection When assigning the Terminal Address, you must use the following convention: Terminals must be allocated a Terminal Address from the choice available (A-F). ● ● Starting with Terminal Address A, you must sequentially assign addresses B, C, etc., for the terminals in the scheme.
Page 146 Chapter 6 - Current Differential Protection P54A/B/C/E |= 0.5 (|I | + |I | + |I bias LOCAL REMOTE1 REMOTE2 Assume a load current of I flowing from end LOCAL to REMOTE1 and REMOTE2. Assume also a high resistance single-end fault of current I , being fed from end LOCAL.
Page 147: Permissive Intertripping
P54A/B/C/E Chapter 6 - Current Differential Protection PERMISSIVE INTERTRIPPING The permissive intertrip (PIT) timer can be set between 0 and 200 ms. This time should be set to provide discrimination with other protection devices. For example, if there is a genuine busbar fault, the time delay should be set to allow busbar protection to clear the fault.
Page 148: Feeders With Small Tapped Loads
Chapter 6 - Current Differential Protection P54A/B/C/E Setting End X End Y End Z Id High Set [p.u.] 3000/200 = 15 3000/200 = 15 3000/200 = 15 Id High Set (Primary) 15*500 = 7500A 15*800 = 12000A 15*200 = 300A Id High Set (Secondary) 15*5 = 75A 15*5 = 75A...
Page 149: Chapter 7 Autoreclose
CHAPTER 7 AUTORECLOSE...
Page 150 Chapter 7 - Autoreclose P54A/B/C/E P54xMED-TM-EN-1...
Page 151: Chapter Overview
P54A/B/C/E Chapter 7 - Autoreclose CHAPTER OVERVIEW Selected models of this product provide sophisticated Autoreclose (AR) functionality. The purpose of this chapter is to describe the operation of this functionality including the principles, logic diagrams and applications. This chapter contains the following sections: Chapter Overview Introduction to Autoreclose Autoreclose Implementation...
Page 152: Introduction To Autoreclose
Chapter 7 - Autoreclose P54A/B/C/E INTRODUCTION TO AUTORECLOSE Approximately 80 - 90% of faults on transmission lines and distribution feeders are transient in nature. This means that most faults do not last long, and are self-clearing if isolated. A common example of a transient fault is an insulator flashover, which may be caused, for example, by lightning, clashing conductors, or wind-blown debris.
Page 153: Autoreclose Implementation
P54A/B/C/E Chapter 7 - Autoreclose AUTORECLOSE IMPLEMENTATION Before describing this function it is first necessary to understand the following terminology: A Shot is an attempt to close a circuit breaker using the Autoreclose function. ● Multi-shot is where more than one Shot is attempted. ●...
Page 154: Autoreclose Logic Inputs From External Sources
Chapter 7 - Autoreclose P54A/B/C/E The Autoreclose function is a logic controller implemented in software. It takes inputs and processes them according to defined logic to generates appropriate outputs. The logic is controlled by user prescribed settings and commands. The controlling logic is complex and so, in order to facilitate its design and understanding, it is decomposed into smaller logic functions which, when combined together implement the complete scheme.
Page 155: Reset Lockout Input
P54A/B/C/E Chapter 7 - Autoreclose It can also be used if an Autoreclose cycle is likely to fail for conditions associated with the protected circuit, such as during the Dead Time, if a circuit breaker indicates that it is not healthy to switch. 3.1.4 RESET LOCKOUT INPUT If a condition that forced a lockout has been removed, the lockout can be reset by energising a logic input...
Page 156: Autoreclose Operating Sequence
Chapter 7 - Autoreclose P54A/B/C/E AUTORECLOSE OPERATING SEQUENCE The Autoreclose sequence is controlled by so-called Dead Timers. Dead Time Control settings are used to select the conditions that initiate Dead Timers in the Autoreclose sequence (for example protection operate, protection reset, CB open, etc.).
Page 157: Ar Timing Sequence - Evolving/Permanent Fault Single-Phase
P54A/B/C/E Chapter 7 - Autoreclose Protection Trip AR in Progress CB Open Dead Time Auto-close Reclaim Time Successful Autoreclose Autoreclose Lockout V03396 Figure 49: Autoreclose sequence for an evolving or permanent fault 3.4.3 AR TIMING SEQUENCE - EVOLVING/PERMANENT FAULT SINGLE-PHASE If the Autorecloser is set for single-phase operation, then single phase operation is only allowed on the first shot.
Page 158: Autoreclose System Map
Chapter 7 - Autoreclose P54A/B/C/E AUTORECLOSE SYSTEM MAP The Autoreclose System Map describes the System Design of the Autoreclose Logic implemented in this product. The Autoreclose is implemented in logical software modules. The logical software modules interact by exchanging signals between themselves, and with other software processes in the product. Interchange between modules is limited to digital signals which are realised as either DDB signals or so called “internal signals”...
Page 159: Figure 51: Key To Logic Diagrams
P54A/B/C/E Chapter 7 - Autoreclose Key: Energising Quantity AND gate & Internal Signal OR gate DDB Signal XOR gate Internal function NOT gate Setting cell Logic 0 Setting value Timer Hardcoded setting Pulse / Latch Measurement Cell SR Latch Internal Calculation SR Latch Reset Dominant Derived setting...
Page 160: Autoreclose System Map Diagrams
Chapter 7 - Autoreclose P54A/B/C/E AUTORECLOSE SYSTEM MAP DIAGRAMS CB Status Time CB Closed 3 ph Protection function 1 Trip Prot AR Block CB Status Input CB Open 3 ph INIT AR Protection function n Trip CB Closed A ph CB Aux 3ph(52-A) IA<...
Page 161: Figure 53: Autoreclose System Map - Part 2
P54A/B/C/E Chapter 7 - Autoreclose External Trip A AR Start Evolve 3Ph CB1L3PAR External Trip B AR Initiation CB1LARIP AR 3pole in prog External Trip C CB ARIP CB1L3PAROK Module 21 External Trip3ph ARIP TMEM3P 3-phase AR cycle selection Inhibit AR CB1LARIP CB1OP2/3P Lockout Alarm...
Page 162: Figure 54: Autoreclose System Map - Part 3
Chapter 7 - Autoreclose P54A/B/C/E Any Trip Set CB Close Res AROK by UI RESCB1 ARSUCC A/R Lockout Auto Close Reset AROK Ind CB Healthy CB Control Res AROK by NoAR CB Open 3 ph Res AROK by Ext CB SCOK Res AROK by Tdly Module 37 CB Fast SCOK...
Page 163: Figure 55: Autoreclose System Map - Part 4
P54A/B/C/E Chapter 7 - Autoreclose CB Control by Control Trip CBM SC CS1 CB Man SCOK Trip Pulse Time CB Trip Fail CBM SC CS2 Man Close Delay Close in Prog CBM SC DLLB Close Pulse Time Control Close CBM SC LLDB CB Healthy Time CB Close Fail CBM SC DLDB...
Page 164: Figure 56: Autoreclose System Map - Part 5
Chapter 7 - Autoreclose P54A/B/C/E Res LO by CB IS RESCB1LO A/R Lockout Pole Discrepancy Res LO by UI Lockout Alarm Reset CB LO Pole Discrepancy Module 62 Res LO by NoAR AR 1pole in prog Pole Discrepancy Num CBs CB Open A ph Res LO by ExtDDB CB Open B ph...
Page 165: Autoreclose Internal Signals
P54A/B/C/E Chapter 7 - Autoreclose AUTORECLOSE INTERNAL SIGNALS The following table lists all the internal signals used in the CB control and Autoreclose logic system: Signal Name Source Module Destination Module Description 3PDTCOMP 3-phase AR Dead Time (25) 3-phase AR Dead Time (25) Three phase dead time complete Force 3-phase Trip (10) 1-pole / 3-pole Trip (13)
Page 166 Chapter 7 - Autoreclose P54A/B/C/E Signal Name Source Module Destination Module Description Signal to force the auto-reclose sequence to DeadLineLockout Dead Time Start Enable (22) Autoreclose Lockout (55) lockout Lockout for 2nd trip after the "Discrim Time" has EVOLVE LOCK Evolving Fault (20) Autoreclose Lockout (55) expired...
Page 167: Autoreclose Ddb Signals
P54A/B/C/E Chapter 7 - Autoreclose Signal Name Source Module Destination Module Description Signal to remember that Autoreclose was TMEM3Ph 1-pole / 3-pole Trip (13) 3-phase AR Cycle Selection (21) initiated by a 3-phase fault Evolving Fault (20) Signal to remember that Autoreclose was TMEMANY 1-pole / 3-pole Trip (13) initiated by an AnyTrip...
Page 168 Chapter 7 - Autoreclose P54A/B/C/E DDB Signal DDB Signal Source Module Destination Module Name Number AR Force 3 pole Force 3-phase Trip (10) CB Trip Conversion AR OK AR In Service 1385 AR Enable (5) AR Modes Enable Autoreclose Lockout Sequence Counter AR Initiation 1543...
Page 169 P54A/B/C/E Chapter 7 - Autoreclose DDB Signal DDB Signal Source Module Destination Module Name Number CB In Service CB Autoclose AR In Progress Evolving Fault CB Closed 3 ph CB State Monitor (1) Reclaim Time Successful AR Signals CB Healthy and System Check Timers CB Control CB Trip Time Monitor CB Closed A ph...
Page 170 Chapter 7 - Autoreclose P54A/B/C/E DDB Signal DDB Signal Source Module Destination Module Name Number 3 Phase AR System Check Check Sync 2 OK Check Sync Signals (60) CB Manual Close System Check Close in Prog CB Control (43) Control Close CB Control (43) Control Trip CB Control (43)
Page 171 P54A/B/C/E Chapter 7 - Autoreclose DDB Signal DDB Signal Source Module Destination Module Name Number External Trip A 1-pole / 3-pole trip, AR In Progress, CB Control External Trip B 1-pole / 3-pole trip, AR In Progress, CB Control External Trip C 1-pole / 3-pole trip, AR In Progress, CB Control External Trip3ph 1-pole / 3-pole trip, AR In Progress, CB Control...
Page 172 Chapter 7 - Autoreclose P54A/B/C/E DDB Signal DDB Signal Source Module Destination Module Name Number AR Modes Enable Force 3-phase Trip Sequence Counter Evolving Fault Seq Counter = 1 Sequence Counter (18) 1-phase AR Dead Time 3-phase AR Dead Time Logic AR Shot Counters 3 Phase AR System Check Force 3-phase Trip...
Page 173: Logic Modules
P54A/B/C/E Chapter 7 - Autoreclose LOGIC MODULES This section contains a complete set of logic diagrams, which will help to explain the Autoreclose function. Most of the logic diagrams shown are logic modules that comprise the overall Autoreclose system. Some of the diagrams shown are not directly related to Autoreclose functionality, however, they may use some inputs are produce outputs that are used by the Autoreclose system.
Page 174: Cb State Monitor Logic Diagram
Chapter 7 - Autoreclose P54A/B/C/E 5.1.1 CB STATE MONITOR LOGIC DIAGRAM CB Aux 3ph(52- A) & CB Aux 3ph(52- B) & CB Closed 3 ph & CB Status Input & 52A 3 pole 52B 3 pole & 52A & 52B 3 pole CB Open 3 ph &...
Page 175: Circuit Breaker Open Logic
P54A/B/C/E Chapter 7 - Autoreclose CIRCUIT BREAKER OPEN LOGIC The Circuit Breaker Open logic module produces internal signals indicating the open status of one or more phases. These signals are used by some of the Autoreclose logic modules. 5.2.1 CIRCUIT BREAKER OPEN LOGIC DIAGRAM CB Open A ph CB Open B ph CB1Op1P...
Page 176: Autoreclose Ok Logic Diagram
Chapter 7 - Autoreclose P54A/B/C/E 5.3.2 AUTORECLOSE OK LOGIC DIAGRAM AR In Service & CB NoAR AR Enable CB CB In Service CB1 AR OK A/R Lockout BAR CB1 V03308 Figure 60: Autoreclose OK logic diagram (Module 8) AUTORECLOSE ENABLE The Autoreclose function must be enabled in the CONFIGURATION column before it can be brought into service.
Page 177: Single-Phase And Three-Phase Autoreclose
P54A/B/C/E Chapter 7 - Autoreclose Single-phase Autoreclosing is permitted only for the first shot of an Autoreclose cycle. In a multi-shot Autoreclose cycle the second and subsequent trips will always be three-phase. For multi-phase faults, you can use the Multi Phase AR setting in the AUTORECLOSE column to configure the following options: ●...
Page 178: Autoreclose Modes Enable Logic Diagram
Chapter 7 - Autoreclose P54A/B/C/E 5.5.2 AUTORECLOSE MODES ENABLE LOGIC DIAGRAM AR In Service & AR Enable CB AR Mode AR 1P & & AR 1/3P CB1 LSPAROK AR 3P AR Opto & CB1L3 PAROK & AR Mode 1 P &...
Page 179 P54A/B/C/E Chapter 7 - Autoreclose Autoreclose cycles can be initiated by: Protection functions internal to the product ● ● A Trip Test feature External protection equipment ● ● Evolving fault combinations Internal Protection Functions Many of the protection functions in the product can be programmed to initiate or block Autoreclose. The associated settings are found in the Autoreclose column and the available options are No Action, Initiate AR, or Block AR.
Page 180: Autoreclose Initiation Logic Diagram
Chapter 7 - Autoreclose P54A/B/C/E 5.7.1 AUTORECLOSE INITIATION LOGIC DIAGRAM Protection function 1 Trip Block AR Initiate AR Prot AR Block Protection function n Trip Block AR Initiate AR INIT AR & IA< Start IB< Start IC< Start AR Trip Test A &...
Page 181: Ar External Trip Initiation Logic Diagram
P54A/B/C/E Chapter 7 - Autoreclose 5.7.3 AR EXTERNAL TRIP INITIATION LOGIC DIAGRAM ≥ TAR2/ 3PH TARANY Init AR & Trip Output A TARA External Trip A Trip AR MemA Init AR & Trip Output B TARB External Trip B Trip AR MemB Init AR &...
Page 182: Protection Reoperation And Evolving Fault Logic Diagram
Chapter 7 - Autoreclose P54A/B/C/E 5.7.4 PROTECTION REOPERATION AND EVOLVING FAULT LOGIC DIAGRAM TMEMANY & 0.02 & Prot ReOp TARANY & Discrim Time & 1P DTime & Evolve Lock Prot ReOp Seq Counter = 1 & Evolve 3Ph LastShot & 0.02 &...
Page 183: Autoreclose In Progress Logic Diagram
P54A/B/C/E Chapter 7 - Autoreclose 5.8.1 AUTORECLOSE IN PROGRESS LOGIC DIAGRAM Init AR AR Start External Trip A External Trip B External Trip C External Trip3 ph TMEM2 /3Ph & TMEM1Ph & AR Initiation & CB1 Op2/3 P CB1L3 PAROK CB ARIP ARIP Inhibit AR...
Page 184: Autoreclose Sequence Counter Logic Diagram
Chapter 7 - Autoreclose P54A/B/C/E 5.9.1 AUTORECLOSE SEQUENCE COUNTER LOGIC DIAGRAM AR Initiation & & ARIP AR Start & 1P Dtime & Seq Counter = 1 Sequence Counter Seq Counter = 0 Increment on rising edge Seq Counter = 1 Reset on falling edge Seq Counter = 2 Single Pole Shot...
Page 185: 3-Phase Autoreclose Cycle Selection
P54A/B/C/E Chapter 7 - Autoreclose 5.10.2 3-PHASE AUTORECLOSE CYCLE SELECTION CB1 L ARIP & CB1 L3 PAROK CB1L 3PAR Evolve 3Ph AR 3 pole in prog TMEM3P CB1 OP2 /3P TMEM ANY & CB1 L SPAROK V03334 Figure 72: Three-phase Autoreclose Cycle Selection logic diagram (Module 21) 5.11 DEAD TIME CONTROL Once an Autoreclose cycle has started, the conditions to enable the dead time to run are determined by the menu...
Page 186: Dead Time Start Enable Logic Diagram
Chapter 7 - Autoreclose P54A/B/C/E 5.11.1 DEAD TIME START ENABLE LOGIC DIAGRAM DT Start by Prot Disable & Protection Reset DTOK All & Protection Op AR Start Dead Line Time & OKTimeSP OK Time 3P & DeadLineLockout ARIP AR Initiation 0.02 Dead Line 3 PDTStart WhenLD...
Page 187: 1-Phase Dead Time Logic Diagram
P54A/B/C/E Chapter 7 - Autoreclose 5.11.2 1-PHASE DEAD TIME LOGIC DIAGRAM CB1LSPAR & DTOK CB 1P & & OKTimeSP Seq Counter = 1 DTOK All AR Start DT Start by Prot & Protection Reset CB1LSPAR CB1OP2/ 3P Logic 1 & CB1LSPAR 1 Pole Dead Time &...
Page 188: 3-Phase Dead Time Logic Diagram
Chapter 7 - Autoreclose P54A/B/C/E 5.11.3 3-PHASE DEAD TIME LOGIC DIAGRAM CB1L 3PAR & DTOK CB1L 3P DTOK All & 3PDTCOMP & OK Time 3P DT Start by Prot Protection Reset & AR Start Logic 1 & CB1L 3PAR 3P AR DT Shot 1 3PDTCOMP &...
Page 189: Circuit Breaker Autoclose Logic Diagram
P54A/B/C/E Chapter 7 - Autoreclose the Autoreclose cycle, or until the next protection operation. These commands are used to initiate the Reclaim Time logic and the Autoreclose Shot Counter logic. 5.12.1 CIRCUIT BREAKER AUTOCLOSE LOGIC DIAGRAM Any Trip & A/ R Lockout &...
Page 190: Prepare Reclaim Initiation Logic Diagram
Chapter 7 - Autoreclose P54A/B/C/E 5.13.1 PREPARE RECLAIM INITIATION LOGIC DIAGRAM CB1SPDTCOMP & SETCB1SPCL Set CB Close CB13 PDTCOMP & CB SCOK & CB Fast SCOK & OK Time 3P SETCB13 PCL V03352 Figure 77: Prepare Reclaim Initiation Logic Diagram (Module 34) 5.13.2 RECLAIM TIME LOGIC DIAGRAM SPAR ReclaimTime...
Page 191: Succesful Autoreclose Signals Logic Diagram
P54A/B/C/E Chapter 7 - Autoreclose 5.13.3 SUCCESFUL AUTORECLOSE SIGNALS LOGIC DIAGRAM 3P Reclaim TComp & 1P Reclaim TComp CB Succ 1P AR SETCB1SPCL & 0.02S CB1OP1 P & CB Closed 3 Ph CB1ARSUCC RESCB1ARSUCC 3P Reclaim TComp & 1P Reclaim TComp CB Succ 3P AR SETCB13 PCL &...
Page 192: Cb Healthy And System Check Timers Logic Diagram
Chapter 7 - Autoreclose P54A/B/C/E healthy signal stays low, then, at the end of the Autoreclose healthy time, a circuit breaker unhealthy alarm is raised. This forces the Autoreclose sequence to be cancelled. Additionally, at the completion of any three-phase dead time, the logic starts an Autoreclose check synchronism timer.
Page 193: Autoreclose Shot Counters Logic Diagram
P54A/B/C/E Chapter 7 - Autoreclose 5.15.1 AUTORECLOSE SHOT COUNTERS LOGIC DIAGRAM Set CB Close Increment CB Total Shots Counter Reset CB Succ 1P AR Increment CB Successful SPAR Shot 1 Counter Reset CB Succ 3P AR & Increment Seq Counter = 1 CB Successful 3PAR Shot 1 Counter Reset &...
Page 194: Circuit Breaker Control
Chapter 7 - Autoreclose P54A/B/C/E 5.16 CIRCUIT BREAKER CONTROL 5.16.1 CB CONTROL LOGIC DIAGRAM CB Control by Opto Note: If the DDB signal CB Healthy is not mapped in PSL it defaults to High . Opto +Local Opto+Remote Opto+Rem+Local Trip Pulse Time HMI Trip Control Trip &...
Page 195: Circuit Breaker Trip Time Monitoring
P54A/B/C/E Chapter 7 - Autoreclose 5.17 CIRCUIT BREAKER TRIP TIME MONITORING The circuit breaker trip time monitoring logic checks for correct circuit breaker tripping following the issue of a protection trip signal. When the protection trip signal is issued, a timer controlled by the Trip Pulse Time setting in the CB CONTROL column is started.
Page 196: Cb Lockout Logic Diagram
Chapter 7 - Autoreclose P54A/B/C/E Circuit breaker failure to close. If a circuit breaker fails to close Autoreclose is blocked and forced to lockout. ● Circuit breaker remains open at the end of the reclaim time. An Autoreclose lockout is forced if the circuit ●...
Page 197: Reset Circuit Breaker Lockout
P54A/B/C/E Chapter 7 - Autoreclose 5.19 RESET CIRCUIT BREAKER LOCKOUT Lockout conditions caused by the circuit breaker condition monitoring functions can be reset according to the condition of the Rst CB mon LO by setting found in the CB CONTROL column. There are two options; CB Close and User interface.
Page 198: Pole Discrepancy
Chapter 7 - Autoreclose P54A/B/C/E 5.20 POLE DISCREPANCY In a three-pole CB, certain combinations of poles open and closed are indicative of a problem. The Pole Discrepancy Logic combines an indication of a Pole Discrepancy condition from the CB Monitoring logic with signals from the internal Autoreclose logic to produce a combined Pole Discrepancy indication for the CB.
Page 199: Cb Trip Conversion Logic Diagram
P54A/B/C/E Chapter 7 - Autoreclose 5.21.1 CB TRIP CONVERSION LOGIC DIAGRAM Trip Inputs A Trip Output A Trip Inputs B Trip Output B Trip Inputs C Trip Output C Tripping Mode & 3 Pole Trip 3 ph AR Force 3 pole Force 3Pole Trip Trip Inputs 3 Ph Dwell...
Page 200: Check Synchronisation Monitor For Cb Closure
Chapter 7 - Autoreclose P54A/B/C/E 5.22.1 CHECK SYNCHRONISATION MONITOR FOR CB CLOSURE System Checks Disabled SysChks Inactive Enabled CS1 Criteria OK & CS2 Criteria OK & CS1 SlipF> Select & CS1 SlipF> CS1 SlipF< & CS1 SlipF< CS2 SlipF> & CS2 SlipF>...
Page 201: Voltage Monitor For Cb Closure
P54A/B/C/E Chapter 7 - Autoreclose 5.22.2 VOLTAGE MONITOR FOR CB CLOSURE System Checks Enabled Live Line & Live Line Dead Line & Dead line Select Live Bus & Live Bus VBus Dead Bus & Dead Bus Voltage Monitors MCB/VTS MCB/VTS CB CS Inhibit LL Inhibit DL Inhibit LB...
Page 202 Chapter 7 - Autoreclose P54A/B/C/E breaker remains closed after the reclaim timer expires, the Autoreclose cycle is complete, and signals are generated to indicate that Autoreclose was successful. These are: CB1 Succ 1P AR (Single-phase Autoreclose CB1) ● CB2 Succ 1P AR (Single-phase Autoreclose CB2) ●...
Page 203: Three-Phase Autoreclose System Check Logic Diagram
P54A/B/C/E Chapter 7 - Autoreclose 5.23.1 THREE-PHASE AUTORECLOSE SYSTEM CHECK LOGIC DIAGRAM CB SC ClsNoDly Enabled & CB Fast SCOK CB SC CS1 Enabled & Check Sync 1 OK CB SC CS2 Enabled & Check Sync 2 OK CB SC DLLB Enabled &...
Page 204: Cb Manual Close System Check Logic Diagram
Chapter 7 - Autoreclose P54A/B/C/E 5.23.2 CB MANUAL CLOSE SYSTEM CHECK LOGIC DIAGRAM CBM SC CS1 Enabled & Check Sync 1 OK CBM SC CS2 Enabled & Check Sync 2 OK CBM SC DLLB Enabled & Dead Line Live Bus CBM SC LLDB Enabled &...
Page 205: Setting Guidelines
P54A/B/C/E Chapter 7 - Autoreclose SETTING GUIDELINES DE-IONISING TIME GUIDANCE The de-ionisation time of a fault arc depends on several factors such as circuit voltage, conductor spacing, fault current and duration, atmospheric conditions, wind speed and capacitive coupling from adjacent conductors. For this reason it is difficult to estimate the de-ionisation time.
Page 206: Reclaim Time Setting Guidelines
Chapter 7 - Autoreclose P54A/B/C/E (a) + (e) - (d) = 50 ms + 280 ms - 85 ms = 245 ms, to allow de-ionising In practice a few additional cycles would be added to allow for tolerances, so Dead Time 1 could be set to 300 ms or greater.
Page 207: Chapter 8 Cb Fail Protection
CHAPTER 8 CB FAIL PROTECTION...
Page 208 Chapter 8 - CB Fail Protection P54A/B/C/E P54xMED-TM-EN-1...
Page 209: Chapter Overview
P54A/B/C/E Chapter 8 - CB Fail Protection CHAPTER OVERVIEW The device provides a Circuit Breaker Fail Protection function. This chapter describes the operation of this function including the principles, logic diagrams and applications. This chapter contains the following sections: Chapter Overview Circuit Breaker Fail Protection Circuit Breaker Fail Implementation Circuit Breaker Fail Logic...
Page 210: Circuit Breaker Fail Protection
Chapter 8 - CB Fail Protection P54A/B/C/E CIRCUIT BREAKER FAIL PROTECTION When a fault occurs, one or more protection devices will operate and issue a trip command to the relevant circuit breakers. Operation of the circuit breaker is essential to isolate the fault and prevent, or at least limit, damage to the power system.
Page 211: Circuit Breaker Fail Implementation
P54A/B/C/E Chapter 8 - CB Fail Protection CIRCUIT BREAKER FAIL IMPLEMENTATION Circuit Breaker Failure Protection is implemented in the CB FAIL & P.DEAD column of the relevant settings group. CIRCUIT BREAKER FAIL TIMERS The circuit breaker failure protection incorporates two timers, CB Fail 1 Timer and CB Fail 2 Timer, allowing configuration for the following scenarios: Simple CBF, where only CB Fail 1 Timer is enabled.
Page 212 Chapter 8 - CB Fail Protection P54A/B/C/E after the circuit breaker in the primary system has opened ensuring that the only current flowing in the AC secondary circuit is the subsidence current. P54xMED-TM-EN-1...
Page 213: Circuit Breaker Fail Logic
P54A/B/C/E Chapter 8 - CB Fail Protection CIRCUIT BREAKER FAIL LOGIC CIRCUIT BREAKER FAIL LOGIC - PART 1 WI Prot Reset Enabled ExtTrip Only Ini Enabled & Aid1 WI Trip 3Ph & Aid2 WI Trip 3Ph WIINFEEDA & Aid 1 WI Trip A &...
Page 214: Circuit Breaker Fail Logic - Part
Chapter 8 - CB Fail Protection P54A/B/C/E CIRCUIT BREAKER FAIL LOGIC - PART 2 External Trip A TripStateExt A Ext Prot Reset I< Only & CB Open & I< Pole Dead A Prot Reset & I< & Prot Reset OR I< Rst OR CBOp &...
Page 215: Circuit Breaker Fail Logic - Part 3
P54A/B/C/E Chapter 8 - CB Fail Protection CIRCUIT BREAKER FAIL LOGIC - PART 3 WIINFEEDA TripStateExtA TripStateA ExtTrip Only Ini Enabled & AnyTripPhaseA IA<FastUndercurrent External Trip 3Ph Ext Prot Reset I< Only & CB Open & I< All Poles Dead Prot Reset &...
Page 216: Figure 93: Circuit Breaker Fail Logic - Part
Chapter 8 - CB Fail Protection P54A/B/C/E CIRCUIT BREAKER FAIL LOGIC - PART 4 From phase B equivalent LatchATripResetIncomp* From phase C equivalent Bfail1 Trip 3ph Latch3PhTripResetIncomp CB Fail Alarm LatchNonITripResetIncomp Bfail2 Trip 3ph CBZCDStateA WIINFEEDA TripStateA & & CB Fail1 Trip A CB Fail 1 Status Enabled CB Fail 1 Timer...
Page 217: Application Notes
P54A/B/C/E Chapter 8 - CB Fail Protection APPLICATION NOTES RESET MECHANISMS FOR CB FAIL TIMERS It is common practise to use low set undercurrent elements to indicate that circuit breaker poles have interrupted the fault or load current. This covers the following situations: ●...
Page 218: Setting Guidelines (Undercurrent)
Chapter 8 - CB Fail Protection P54A/B/C/E CBF resets: 1. Undercurrent element asserts 2. Undercurrent element asserts and the breaker status indicates an open position 3. Protection resets and the undercurrent element asserts Fault occurs Safety Protection Maximum breaker reset margin operating time clearing time...
Page 219: Chapter 9 Current Protection Functions
CHAPTER 9 CURRENT PROTECTION FUNCTIONS...
Page 220 Chapter 9 - Current Protection Functions P54A/B/C/E P54xMED-TM-EN-1...
Page 221: Chapter Overview
P54A/B/C/E Chapter 9 - Current Protection Functions CHAPTER OVERVIEW The primary purpose of this product is not overcurrent protection. It does however provide a range of current protection functions to be used as backup protection. This chapter assumes you are familiar with overcurrent protection principles and does not provide detailed information here.
Page 222: Phase Fault Overcurrent Protection
Chapter 9 - Current Protection Functions P54A/B/C/E PHASE FAULT OVERCURRENT PROTECTION Phase fault overcurrent protection is provided as a form of back-up protection that could be: Permanently disabled ● Permanently enabled ● ● Enabled only in case of VT fuse/MCB failure Enabled only in case of protection communication channel failure ●...
Page 223 P54A/B/C/E Chapter 9 - Current Protection Functions Phase of protection Operate current Polarizing voltage B Phase C Phase Under system fault conditions, the fault current vector lags its nominal phase voltage by an angle depending on the system X/R ratio. The IED must therefore operate with maximum sensitivity for currents lying in this region. This is achieved by using the IED characteristic angle (RCA).
Page 224: Poc Logic
Chapter 9 - Current Protection Functions P54A/B/C/E POC LOGIC I>1 Start A I>1 Current Set & & I>1 Trip A I>1 Direction Directional check VTS Fast Block Timer Settings & I> Blocking VTS Blocks I>1 I>1 Start B I>1 Current Set &...
Page 225: Negative Sequence Overcurrent Protection
P54A/B/C/E Chapter 9 - Current Protection Functions NEGATIVE SEQUENCE OVERCURRENT PROTECTION When applying standard phase overcurrent protection, the overcurrent elements must be set significantly higher than the maximum load current. This limits the element’s sensitivity. Most protection schemes also use an earth fault element operating from residual current, which improves sensitivity for earth faults.
Page 226: Npsoc Logic
Chapter 9 - Current Protection Functions P54A/B/C/E NPSOC LOGIC I2>1 Start IDMT/DT I2>1 Current Set & & & I2>1 trip CTS Block I2 > Inhibit I2 >1 Direction Directional I2> V2pol Set check VTS Slow block I 2> VTS Blocking &...
Page 227: Setting Guidelines (Directional Element)
P54A/B/C/E Chapter 9 - Current Protection Functions 3.4.3 SETTING GUIDELINES (DIRECTIONAL ELEMENT) Where negative phase sequence current may flow in either direction through an IED location, such as parallel lines or ring main systems, directional control of the element should be employed (VT models only). Directionality is achieved by comparing the angle between the negative phase sequence voltage and the negative phase sequence current and the element may be selected to operate in either the forward or reverse direction.
Page 228: Earth Fault Protection
Chapter 9 - Current Protection Functions P54A/B/C/E EARTH FAULT PROTECTION Earth faults are overcurrent faults where the fault current flows to earth. Earth faults are the most common type of fault. Earth faults can be measured directly from the system by means of: ●...
Page 229: Directional Element
P54A/B/C/E Chapter 9 - Current Protection Functions is the operating time I is the measured current IN> Setting is an adjustable setting, which defines the start point of the characteristic Note: Although the start point of the characteristic is defined by the "ΙN>" setting, the actual current threshold is a different setting called "IDG Ιs".
Page 230: Negative Sequence Polarisation
Chapter 9 - Current Protection Functions P54A/B/C/E Small levels of residual voltage could be present under normal system conditions due to system imbalances, VT inaccuracies, device tolerances etc. For this reason, the device includes a user settable threshold (IN> VNPol set), which must be exceeded in order for the DEF function to become operational.
Page 231: Earth Fault Protection Logic
P54A/B/C/E Chapter 9 - Current Protection Functions EARTH FAULT PROTECTION LOGIC IN>1 Start IDMT/ DT IN>1 Current Set & & & IN>1 Trip CTS Block Inhibit IN >1 IN>1 Directional IN> VNpol Set Directional check Low Current Residual voltage polarisation VTS Slow Block &...
Page 232 Chapter 9 - Current Protection Functions P54A/B/C/E We recommend the following RCA settings: Resistance earthed systems: 0° ● ● Distribution systems (solidly earthed): -45° Transmission systems (solidly earthed): -60° ● P54xMED-TM-EN-1...
Page 233: Sensitive Earth Fault Protection
P54A/B/C/E Chapter 9 - Current Protection Functions SENSITIVE EARTH FAULT PROTECTION With some earth faults, the fault current flowing to earth is limited by either intentional resistance (as is the case with some HV systems) or unintentional resistance (e.g. in very dry conditions and where the substrate is high resistance, such as sand or rock).
Page 234: Sensitive Earth Fault Protection Logic
Chapter 9 - Current Protection Functions P54A/B/C/E EPATR Curve 1000 1000 Current in Primary A (CT Ratio 100A/1A) V00616 Figure 102: EPATR B characteristic shown for TMS = 1.0 SENSITIVE EARTH FAULT PROTECTION LOGIC IN>1 Start IDMT/ DT ISEF>1 Current &...
Page 235: Application Notes
P54A/B/C/E Chapter 9 - Current Protection Functions APPLICATION NOTES 5.4.1 INSULATED SYSTEMS When insulated systems are used, it is not possible to detect faults using standard earth fault protection. It is possible to use a residual overvoltage device to achieve this, but even with this method full discrimination is not possible.
Page 236: Setting Guidelines (Insulated Systems)
Chapter 9 - Current Protection Functions P54A/B/C/E Restrain Vapf Operate Vcpf Vbpf Vres (= 3Vo) An RCA setting of ±90º shifts the IR3 = (IH1 + IH2) “centre of the characteristic” to here E00628 Figure 105: Phasor diagrams for insulated system with C phase fault The current imbalance detected by a core balanced current transformer on the healthy feeders is the vector addition of Ia1 and Ib1.
Page 237: Figure 106: Positioning Of Core Balance Current Transformers
P54A/B/C/E Chapter 9 - Current Protection Functions Cable gland Cable box Cable gland/shealth earth connection “Incorrect” No operation “Correct” Operation E00614 Figure 106: Positioning of core balance current transformers If the cable sheath is terminated at the cable gland and directly earthed at that point, a cable fault (from phase to sheath) will not result in any unbalanced current in the core balance CT.
Page 238: High Impedance Ref
Chapter 9 - Current Protection Functions P54A/B/C/E HIGH IMPEDANCE REF The device provides a high impedance restricted earth fault protection function. An external resistor is required to provide stability in the presence of saturated line current transformers. Current transformer supervision signals do not block the high impedance REF protection.
Page 239: Figure 108: High Impedance Ref Connection
P54A/B/C/E Chapter 9 - Current Protection Functions Phase A Phase A Phase B Phase B Phase C Phase C Phase A Phase B Phase C STAB Neutral Neutral STAB Connecting IED to star winding for High Connecting IED to delta winding for High Impedance REF Impedance REF V00680...
Page 240: Thermal Overload Protection
Chapter 9 - Current Protection Functions P54A/B/C/E THERMAL OVERLOAD PROTECTION The heat generated within an item of plant is the resistive loss. The thermal time characteristic is therefore based on the equation I Rt. Over-temperature conditions occur when currents in excess of their maximum rating are allowed to flow for a period of time.
Page 241: Thermal Overload Protection Implementation
P54A/B/C/E Chapter 9 - Current Protection Functions THERMAL OVERLOAD PROTECTION IMPLEMENTATION The device incorporates a current-based thermal characteristic, using RMS load current to model heating and cooling of the protected plant. The element can be set with both alarm and trip stages. Thermal Overload Protection is implemented in the THERMAL OVERLOAD column of the relevant settings group.
Page 242: Figure 110: Spreadsheet Calculation For Dual Time Constant Thermal Characteristic
Chapter 9 - Current Protection Functions P54A/B/C/E Figures based on equation E00728 Figure 110: Spreadsheet calculation for dual time constant thermal characteristic 100000 Time constant 1 = 5 mins 10000 Time constant 2 = 120 mins Pre-overload current = 0.9 pu Thermal setting = 1 Amp 1000 Current as a Multiple of Thermal Setting...
Page 243: Setting Guidelines For Single Time Constant Characteristic
P54A/B/C/E Chapter 9 - Current Protection Functions Note: The thermal time constants given in the above tables are typical only. Reference should always be made to the plant manufacturer for accurate information. 7.5.2 SETTING GUIDELINES FOR SINGLE TIME CONSTANT CHARACTERISTIC The time to trip varies depending on the load current carried before application of the overload, i.e.
Page 244 Chapter 9 - Current Protection Functions P54A/B/C/E P54xMED-TM-EN-1...
Page 245: Broken Conductor Protection
P54A/B/C/E Chapter 9 - Current Protection Functions BROKEN CONDUCTOR PROTECTION One type of unbalanced fault is the 'Series' or 'Open Circuit' fault. This type of fault can arise from, among other things, broken conductors. Series faults do not cause an increase in phase current and so cannot be detected by overcurrent protection.
Page 246 Chapter 9 - Current Protection Functions P54A/B/C/E Note: A minimum value of 8% negative phase sequence current is required for successful operation. Since sensitive settings have been employed, we can expect that the element will operate for any unbalanced condition occurring on the system (for example, during a single pole autoreclose cycle). For this reason, a long time delay is necessary to ensure co-ordination with other protection devices.
Page 247: Chapter 10 Voltage Protection Functions
CHAPTER 10 VOLTAGE PROTECTION FUNCTIONS...
Page 248 Chapter 10 - Voltage Protection Functions P54A/B/C/E P54xMED-TM-EN-1...
Page 249: Chapter Overview
P54A/B/C/E Chapter 10 - Voltage Protection Functions CHAPTER OVERVIEW The device provides a wide range of voltage protection functions. This chapter describes the operation of these functions including the principles, logic diagrams and applications. This chapter contains the following sections: Chapter Overview Undervoltage Protection Overvoltage Protection...
Page 250: Undervoltage Protection
Chapter 10 - Voltage Protection Functions P54A/B/C/E UNDERVOLTAGE PROTECTION Undervoltage conditions may occur on a power system for a variety of reasons, some of which are outlined below: Undervoltage conditions can be related to increased loads, whereby the supply voltage will decrease in ●...
Page 251: Undervoltage Protection Logic
P54A/B/C/E Chapter 10 - Voltage Protection Functions UNDERVOLTAGE PROTECTION LOGIC V< Measur't Mode V<1 Start A/AB & V<1 Voltage Set & V <1 Trip A/AB V<1 Time Delay V< Measur't Mode V<1 Start B/BC & V<1 Voltage Set & V<1 Trip B/BC V<1 Time Delay V<...
Page 252: Application Notes
Chapter 10 - Voltage Protection Functions P54A/B/C/E open circuit breaker via auxiliary contacts feeding the opto-inputs or it detects a combination of both undercurrent and undervoltage on any one phase. APPLICATION NOTES 2.3.1 UNDERVOLTAGE SETTING GUIDELINES In most applications, undervoltage protection is not required to operate during system earth fault conditions. If this is the case you should select phase-to-phase voltage measurement, as this quantity is less affected by single- phase voltage dips due to earth faults.
Page 253: Overvoltage Protection
P54A/B/C/E Chapter 10 - Voltage Protection Functions OVERVOLTAGE PROTECTION Overvoltage conditions are generally related to loss of load conditions, whereby the supply voltage increases in magnitude. This situation would normally be rectified by voltage regulating equipment such as AVRs (Auto Voltage Regulators) or On Load Tap Changers.
Page 254: Overvoltage Protection Logic
Chapter 10 - Voltage Protection Functions P54A/B/C/E OVERVOLTAGE PROTECTION LOGIC V> Measur't Mode V>1 Start A/AB & V >1 Trip A/AB V>1 Voltage Set V>1 Time Delay V> Measur't Mode V>1 Start B/BC & V>1 Trip B/BC V>1 Voltage Set V>1 Time Delay V>...
Page 255: Application Notes
P54A/B/C/E Chapter 10 - Voltage Protection Functions APPLICATION NOTES 3.3.1 OVERVOLTAGE SETTING GUIDELINES The provision of multiple stages and their respective operating characteristics allows for a number of possible applications: Definite Time can be used for both stages to provide the required alarm and trip stages. ●...
Page 256: Compensated Overvoltage
Chapter 10 - Voltage Protection Functions P54A/B/C/E COMPENSATED OVERVOLTAGE The Compensated Overvoltage function calculates the positive sequence voltage at the remote terminal using the positive sequence local current and voltage and the line impedance and susceptance. This can be used on long transmission lines where Ferranti Overvoltages can develop under remote circuit breaker open conditions.
Page 257: Residual Overvoltage Protection
P54A/B/C/E Chapter 10 - Voltage Protection Functions RESIDUAL OVERVOLTAGE PROTECTION On a healthy three-phase power system, the sum of the three-phase to earth voltages is nominally zero, as it is the vector sum of three balanced vectors displaced from each other by 120°. However, when an earth fault occurs on the primary system, this balance is upset and a residual voltage is produced.
Page 258: Residual Overvoltage Logic
Chapter 10 - Voltage Protection Functions P54A/B/C/E RESIDUAL OVERVOLTAGE LOGIC VN>1 Start & VN>1 Voltage Set & IDMT/DT VN>1 Trip VTS Fast Block VN>1 Timer Blk V00802 Figure 115: Residual Overvoltage logic The Residual Overvoltage module (VN>) is a level detector that detects when the voltage magnitude exceeds a set threshold, for each stage.
Page 259: Calculation For Impedance Earthed Systems
P54A/B/C/E Chapter 10 - Voltage Protection Functions X 3 E + 2Z E00800 Figure 116: Residual voltage for a solidly earthed system As can be seen from the above diagram, the residual voltage measured on a solidly earthed system is solely dependent on the ratio of source impedance behind the protection to the line impedance in front of the protection, up to the point of fault.
Page 260: Setting Guidelines
Chapter 10 - Voltage Protection Functions P54A/B/C/E X 3 E + 2Z + 3Z E00801 Figure 117: Residual voltage for an impedance earthed system An impedance earthed system will always generate a relatively large degree of residual voltage, as the zero sequence source impedance now includes the earthing impedance.
Page 261: Chapter 11 Frequency Protection Functions
CHAPTER 11 FREQUENCY PROTECTION FUNCTIONS...
Page 262 Chapter 11 - Frequency Protection Functions P54A/B/C/E P54xMED-TM-EN-1...
Page 263: Chapter Overview
P54A/B/C/E Chapter 11 - Frequency Protection Functions CHAPTER OVERVIEW The device provides a range of frequency protection functions. This chapter describes the operation of these functions including the principles, logic diagrams and applications. This chapter contains the following sections: Chapter Overview Frequency Protection Independent R.O.C.O.F Protection P54xMED-TM-EN-1...
Page 264: Frequency Protection
Chapter 11 - Frequency Protection Functions P54A/B/C/E FREQUENCY PROTECTION Power generation and utilisation needs to be well balanced in any industrial, distribution or transmission network. These electrical networks are dynamic entities, with continually varying loads and supplies, which are continually affecting the system frequency.
Page 265: Underfrequency Protection Logic
P54A/B/C/E Chapter 11 - Frequency Protection Functions 2.1.2 UNDERFREQUENCY PROTECTION LOGIC Freq Freq 1155 Averaging Averaging F<1 Start F<1 Start 1161 & F<1 Setting F<1 Setting F<1 Trip F<1 Trip F<1 Status F<1 Status Enabled Enabled All Poles Dead All Poles Dead 1370 Freq Not Found Freq Not Found...
Page 266: Overfrequency Protection Logic
Chapter 11 - Frequency Protection Functions P54A/B/C/E 2.2.2 OVERFREQUENCY PROTECTION LOGIC 1159 Averaging F>1 Start F>1 Start Freq Freq 1165 F>1 Setting F>1 Setting & F>1 Trip F>1 Trip F>1 Status F>1 Status Enabled Enabled All Poles Dead All Poles Dead 1370 Freq Not Found Freq Not Found...
Page 267: Independent R.o.c.o.f Protection
P54A/B/C/E Chapter 11 - Frequency Protection Functions INDEPENDENT R.O.C.O.F PROTECTION Where there are very large loads, imbalances may occur that result in rapid decline in system frequency. The situation could be so bad that shedding one or two stages of load is unlikely to stop this rapid frequency decline. In such a situation, standard underfrequency protection will normally have to be supplemented with protection that responds to the rate of change of frequency.
Page 268 Chapter 11 - Frequency Protection Functions P54A/B/C/E P54xMED-TM-EN-1...
Page 269: Chapter 12 Monitoring And Control
CHAPTER 12 MONITORING AND CONTROL...
Page 270 Chapter 12 - Monitoring and Control P54A/B/C/E P54xMED-TM-EN-1...
Page 271: Chapter Overview
P54A/B/C/E Chapter 12 - Monitoring and Control CHAPTER OVERVIEW As well as providing a range of protection functions, the product includes comprehensive monitoring and control functionality. This chapter contains the following sections: Chapter Overview Event Records Disturbance Recorder Measurements CB Condition Monitoring CB State Monitoring Circuit Breaker Control Pole Dead Function...
Page 272: Event Records
Chapter 12 - Monitoring and Control P54A/B/C/E EVENT RECORDS General Electric devices record events in an event log. This allows you to establish the sequence of events that led up to a particular situation. For example, a change in a digital input signal or protection element output signal would cause an event record to be created and stored in the event log.
Page 273: Opto-Input Events
P54A/B/C/E Chapter 12 - Monitoring and Control Standard events are further sub-categorised internally to include different pieces of information. These are: Protection events (starts and trips) ● ● Maintenance record events Platform events ● Note: The first event in the list (event 0) is the most recent event to have occurred. 2.1.1 OPTO-INPUT EVENTS If one or more of the opto-inputs has changed state since the last time the protection algorithm ran (which runs at...
Page 274: Fault Record Events
Chapter 12 - Monitoring and Control P54A/B/C/E 2.1.4 FAULT RECORD EVENTS An event record is created for every fault the IED detects. This is also known as a fault record. The event type description shown in the Event Text cell for this type of event is always Fault Recorded. The IED contains a separate register containing the latest fault records.
Page 275: Security Events
P54A/B/C/E Chapter 12 - Monitoring and Control The Event Value cell for this type of event is a 32 bit binary string representing the state of the relevant DDB signals. These binary strings can also be viewed in the COMMISSION TESTS column in the relevant DDB batch cells. Not all DDB signals can generate an event.
Page 276: Disturbance Recorder
Chapter 12 - Monitoring and Control P54A/B/C/E DISTURBANCE RECORDER The disturbance recorder feature allows you to record selected current and voltage inputs to the protection elements, together with selected digital signals. The digital signals may be inputs, outputs, or internal DDB signals. The disturbance records can be extracted using the disturbance record viewer in the settings application software.
Page 277: Measurements
P54A/B/C/E Chapter 12 - Monitoring and Control MEASUREMENTS MEASURED QUANTITIES The device measures directly and calculates a number of system quantities, which are updated every second. You can view these values in the relevant MEASUREMENT columns or with the Measurement Viewer in the settings application software.
Page 278: Cb Condition Monitoring
Chapter 12 - Monitoring and Control P54A/B/C/E CB CONDITION MONITORING The device records various statistics related to each circuit breaker trip operation, allowing an accurate assessment of the circuit breaker condition to be determined. These statistics are available in the CB CONDITION column.
Page 279: Broken Current Accumulator
P54A/B/C/E Chapter 12 - Monitoring and Control BROKEN CURRENT ACCUMULATOR PhaseACurrent Set Cumulative IA broken In Reset PhaseBCurrent Set Cumulative IB broken In Reset PhaseCCurrent Set Cumulative IC broken In Trip 3 ph Reset External Trip3 ph Note: Broken current totals not incremented when device is in test mode Trip Output A External Trip A Trip Output B...
Page 280: Cb Operating Time Accumulator
Chapter 12 - Monitoring and Control P54A/B/C/E CB OPERATING TIME ACCUMULATOR Trip 3 ph Note : CB operating time not accumulated when device is in test mode External Trip3 ph Trip Output A Start CB operating time phase A Increment External Trip A Stop CBOpTimePhA Counter...
Page 281: Reset Lockout Alarm
P54A/B/C/E Chapter 12 - Monitoring and Control RESET LOCKOUT ALARM CB mon LO reset Reset Lockout Alarm Clear Alarms CB Failed to Trip & CB Open 3 ph Lockout Alarm CB Closed 3 ph CB Closed A ph CB Closed B ph &...
Page 282: Cb Condition Monitoring Logic
Chapter 12 - Monitoring and Control P54A/B/C/E CB CONDITION MONITORING LOGIC I^ Maintenance Alarm Enabled & & CB I^ Maint Greatest broken current total I^ Maintenance CB Monitor Alarm I^ Lockout Alarm Enabled & CB I^ Lockout I^ Lockout No. CB Ops Maint Alarm Enabled &...
Page 283: Reset Cb Lockout Logic Diagram
P54A/B/C/E Chapter 12 - Monitoring and Control If set to CB Close, a timer setting, CB mon LO RstDly, becomes visible. When the circuit breaker closes, the CB mon LO RstDly time starts. The lockout is reset when the timer expires. If set to User Interface then a command, CB mon LO reset, becomes visible.
Page 284: Setting The Thresholds For The Number Of Operations
Chapter 12 - Monitoring and Control P54A/B/C/E may be slower than would normally be expected. The Total Current Accumulator (I^ counter) cumulatively stores the total value of the current broken by the circuit breaker providing a more accurate assessment of the circuit breaker condition.
Page 285: Cb State Monitoring
P54A/B/C/E Chapter 12 - Monitoring and Control CB STATE MONITORING CB State monitoring is used to verify the open or closed state of a circuit breaker. Most circuit breakers have auxiliary contacts through which they transmit their status (open or closed) to control equipment such as IEDs. These auxiliary contacts are known as: 52A for contacts that follow the state of the CB ●...
Page 286: Cb State Monitor Logic Diagram
Chapter 12 - Monitoring and Control P54A/B/C/E CB STATE MONITOR LOGIC DIAGRAM CB Aux 3ph(52- A) & CB Aux 3ph(52- B) & CB Closed 3 ph & CB Status Input & 52A 3 pole 52B 3 pole & 52A & 52B 3 pole CB Open 3 ph &...
Page 287: Circuit Breaker Control
P54A/B/C/E Chapter 12 - Monitoring and Control CIRCUIT BREAKER CONTROL Although some circuit breakers do not provide auxiliary contacts, most provide auxiliary contacts to reflect the state of the circuit breaker. These are: CBs with 52A contacts (where the auxiliary contact follows the state of the CB) ●...
Page 288: Cb Control Using The Hotkeys
Chapter 12 - Monitoring and Control P54A/B/C/E For this to work you have to set the CB control by cell to option 1 Local, option 3 Local + Remote, option 5 Opto+Local, or option 7 Opto+Local+Remote in the CB CONTROL column. CB CONTROL USING THE HOTKEYS The hotkeys allow you to manually trip and close the CB without the need to enter the SYSTEM DATA column.
Page 289: Cb Control Using The Opto-Inputs
P54A/B/C/E Chapter 12 - Monitoring and Control default PSL is set up such that Function key 2 initiates a trip and Function key 3 initiates a close. For this to work you have to set the CB control by cell to option 5 Opto+Local, or option 7 Opto+Local+Remote in the CB CONTROL column.
Page 290: Cb Healthy Check
Chapter 12 - Monitoring and Control P54A/B/C/E Protection Trip Trip Remote Control Trip Close Remote Control Close Local Remote Close Trip E01207 Figure 132: Remote Control of Circuit Breaker CB HEALTHY CHECK A CB Healthy check is available if required. This facility accepts an input to one of the opto-inputs to indicate that the breaker is capable of closing (e.g.
Page 291: Cb Control Logic Diagram
P54A/B/C/E Chapter 12 - Monitoring and Control Following manual circuit breaker closure, if either a single phase or a three phase fault occur, the circuit breaker is tripped three phase, but Autoreclose is not locked out for this condition. CB CONTROL LOGIC DIAGRAM CB Control by Opto Note: If the DDB signal CB Healthy is not mapped in PSL it defaults to High .
Page 292: Pole Dead Function
Chapter 12 - Monitoring and Control P54A/B/C/E POLE DEAD FUNCTION The Pole Dead Logic is used to determine and indicate that one or more phases of the line are not energised. A Pole Dead condition is determined either by measuring: the line currents and/or voltages, or ●...
Page 293: System Checks
P54A/B/C/E Chapter 12 - Monitoring and Control SYSTEM CHECKS In some situations it is possible for both "bus" and "line" sides of a circuit breaker to be live when a circuit breaker is open - for example at the ends of a feeder that has a power source at each end. Therefore, it is normally necessary to check that the network conditions on both sides are suitable, before closing the circuit breaker.
Page 294: Voltage Monitoring
Chapter 12 - Monitoring and Control P54A/B/C/E The Check Sync VT may be connected to one of the phase-to-phase voltages or phase-to-neutral voltages. This needs to be defined using the CS Input setting in the CT AND VT RATIOS column. Options are, A-B, B-C, C-A, A-N, B- N, or C-N.
Page 295: Figure 135: Check Synchronisation Vector Diagram
P54A/B/C/E Chapter 12 - Monitoring and Control 0º Check Sync Stage 2 Limits Check Sync Stage 1 Limits Live Volts Rotating Vector Nomical Volts V LINE Dead Volts ±180º System Split E01204 Limits Figure 135: Check Synchronisation vector diagram P54xMED-TM-EN-1...
Page 296: Voltage Monitor For Cb Closure
Chapter 12 - Monitoring and Control P54A/B/C/E VOLTAGE MONITOR FOR CB CLOSURE System Checks Enabled Live Line & Live Line Dead Line & Dead line Select Live Bus & Live Bus VBus Dead Bus & Dead Bus Voltage Monitors MCB/VTS MCB/VTS CB CS Inhibit LL Inhibit DL...
Page 297: Check Synchronisation Monitor For Cb Closure
P54A/B/C/E Chapter 12 - Monitoring and Control CHECK SYNCHRONISATION MONITOR FOR CB CLOSURE System Checks Disabled SysChks Inactive Enabled CS1 Criteria OK & CS2 Criteria OK & CS1 SlipF> Select & CS1 SlipF> CS1 SlipF< & CS1 SlipF< CS2 SlipF> &...
Page 298: System Check Psl
Chapter 12 - Monitoring and Control P54A/B/C/E SYSTEM CHECK PSL SysChks Inactive Check Sync 1 OK Check Sync 2 OK Man Check Synch Live Line & Dead Bus AR Sys Checks & Dead Line & Live Bus V02028 Figure 138: System Check PSL APPLICATION NOTES 9.5.1 PREDICTIVE CLOSURE OF CIRCUIT BREAKER...
Page 299 P54A/B/C/E Chapter 12 - Monitoring and Control 220/√3 110/√3 220/√3 0.577 0º 220/√3 110/√3 220/√3 110/3 1.732 0º P54xMED-TM-EN-1...
Page 300 Chapter 12 - Monitoring and Control P54A/B/C/E P54xMED-TM-EN-1...
Page 301: Chapter 13 Supervision
CHAPTER 13 SUPERVISION...
Page 302 Chapter 13 - Supervision P54A/B/C/E P54xMED-TM-EN-1...
Page 303: Chapter Overview
P54A/B/C/E Chapter 13 - Supervision CHAPTER OVERVIEW This chapter describes the supervison functions. This chapter contains the following sections: Chapter Overview Current Differential Supervision Voltage Transformer Supervision Current Transformer Supervision Trip Circuit Supervision P54xMED-TM-EN-1...
Page 304: Current Differential Supervision
Chapter 13 - Supervision P54A/B/C/E CURRENT DIFFERENTIAL SUPERVISION Current Differential protection of transmission lines or distribution feeders requires communication of measured values of currents between terminals so that a comparison of current entering and leaving the protected zone can be made. To determine the health of the protected zone, the current values received from a remote terminal must be synchronised to locally acquired values.
Page 305 P54A/B/C/E Chapter 13 - Supervision If a starter element picks up, the associated DDB signal is asserted. These can be used to block the current differential protection. These DDB signals are: I1 Lo Start (Positive phase-sequence fixed threshold start) ● Del I1 Lo Start (Rate-of-change of positive phase-sequence current) ●...
Page 306: Current Differential Starter Supervision Logic
Chapter 13 - Supervision P54A/B/C/E 2.1.1 CURRENT DIFFERENTIAL STARTER SUPERVISION LOGIC & I1 Lo Start Start I1 low Start I1 Disabled 1/ 8 cycle I1 Delta Del I1 Lo Start Delta I1 low & Block Delta Delta I1 Disabled Reset Low Time &...
Page 307: Current Differential Start Logic
P54A/B/C/E Chapter 13 - Supervision 2.1.2 CURRENT DIFFERENTIAL START LOGIC The Permit Cdiff internal signal interacts with the Current Differential function to control the Current Differential start signals. the following figure shows how this is achieved for the line differential currents. The same principle applies to neutral differential current.
Page 308: Communications Asymmetry Supervision
Chapter 13 - Supervision P54A/B/C/E Idiff Normal Tripping Characteristic Supervised Tripping Characteristic Operate Region K2 slope Supervise Region Restrain K1 Slope Region Ibias V02603 Figure 141: Switched Communication Path supervision The change to the characteristic is determined by two timers (Char Mod Time, and Char Mod RstTime) found in the PROT COMMS/IM64 column.
Page 309: Figure 142: Communication Asymmetry Supervision
P54A/B/C/E Chapter 13 - Supervision changed to prevent tripping should the effect of increasing load current with communications asymmetry take the apparent differential current above the operate threshold. Referring to the Switched Communication Path Supervision feature, if communication switching takes place, the Current Differential protection will detect a propagation delay change and invoke a temporary increase in the tripping threshold for a period set in the Char Mod Time setting column.
Page 310: Voltage Transformer Supervision
Chapter 13 - Supervision P54A/B/C/E VOLTAGE TRANSFORMER SUPERVISION The Voltage Transformer Supervision (VTS) function is used to detect failure of the AC voltage inputs to the protection. This may be caused by voltage transformer faults, overloading, or faults on the wiring, which usually results in one or more of the voltage transformer fuses blowing.
Page 311: Vts Implementation
P54A/B/C/E Chapter 13 - Supervision following line energization (based on an All Poles Dead signal drop off). It must still be set in excess of any non- fault based currents on line energisation (load, line charging current, transformer inrush current if applicable), but below the level of current produced by a close-up three-phase fault.
Page 312 Chapter 13 - Supervision P54A/B/C/E P54xMED-TM-EN-1...
Page 313: Vts Logic
P54A/B/C/E Chapter 13 - Supervision VTS LOGIC All Poles Dead 240ms VTS I> Inhibit & VTS I> Inhibit VTS I> Inhibit VTS Time Delay Hardcoded threshold & Hardcoded threshold & VTS Slow Block Hardcoded threshold Delta IA & & VTS Fast Block Hardcoded threshold Delta IB Hardcoded threshold...
Page 314: Figure 143: Vts Logic
Chapter 13 - Supervision P54A/B/C/E Figure 143: VTS logic The IED may respond as follows, on operation of any VTS element: ● VTS set to provide alarm indication only Optional blocking of voltage-dependent protection elements ● Optional conversion of directional overcurrent elements to non-directional protection (by setting the ●...
Page 315: Current Transformer Supervision
P54A/B/C/E Chapter 13 - Supervision CURRENT TRANSFORMER SUPERVISION The Current Transformer Supervision function (CTS) is used to detect failure of the AC current inputs to the protection. This may be caused by internal current transformer faults, overloading, or faults on the wiring. If there is a failure of the AC current input, the protection could misinterpret this as a failure of the actual phase currents on the power system, which could result in maloperation.
Page 316: Differential Cts Logic
Chapter 13 - Supervision P54A/B/C/E DIFFERENTIAL CTS LOGIC Inhibit CTS & Any Trip Disable CTS CT1 L i1> > CT1 R1 i1> CT1 R2 i1> CT1 L i2/i1>> CTS Time Delay CTS Status Indication CT1 R1 i2/i1> & Pickup CT Fail Alarm &...
Page 317: Standard Cts Logic
P54A/B/C/E Chapter 13 - Supervision The CTS function is implemented in the SUPERVISION column of the relevant settings group, under the sub-heading CT SUPERVISION. The following settings are relevant for CT Supervision: CTS Status: to disable or enable CTS ● CTS VN<...
Page 318: Differential Cts Setting Guidelines
Chapter 13 - Supervision P54A/B/C/E 4.6.2 DIFFERENTIAL CTS SETTING GUIDELINES The Phase Is1 CTS setting must be set above the phase current of the maximum load transfer expected, normally at 1.2 In. This setting defines the minimum pick-up level of the current differential protection once the current transformer supervision CTS is detected.
Page 319: Trip Circuit Supervision
P54A/B/C/E Chapter 13 - Supervision TRIP CIRCUIT SUPERVISION In most protection schemes, the trip circuit extends beyond the IED enclosure and passes through components such as links, relay contacts, auxiliary switches and other terminal boards. Such complex arrangements may require dedicated schemes for their supervision. There are two distinctly separate parts to the trip circuit;...
Page 320: Psl For Tcs Scheme 1
Chapter 13 - Supervision P54A/B/C/E Trip Circuit Voltage Opto Voltage Setting with R1 Fitted Resistor R1 (ohms) 110/125 48/54 2.7k 220/250 110/125 5.2k Warning: This Scheme is not compatible with Trip Circuit voltages of less than 48 V. 5.1.2 PSL FOR TCS SCHEME 1 Opto Input dropoff *Output Relay...
Page 321: Figure 146: Tcs Scheme
P54A/B/C/E Chapter 13 - Supervision Trip Output Relay Trip coil Trip path Opto-input 1 Circuit Breaker Opto-input 2 V01215 Figure 148: TCS Scheme 2 When the breaker is closed, supervision current passes through opto input 1 and the trip coil. When the breaker is open current flows through opto input 2 and the trip coil.
Page 322: Figure 150: Tcs Scheme 3
Chapter 13 - Supervision P54A/B/C/E Output Relay Trip coil Trip path Opto-input Circuit Breaker V01216 Figure 150: TCS Scheme 3 When the CB is closed, supervision current passes through the opto-input, resistor R2 and the trip coil. When the CB is open, current flows through the opto-input, resistors R1 and R2 (in parallel), resistor R3 and the trip coil. The supervision current is maintained through the trip path with the breaker in either state, therefore providing pre- closing supervision.
Page 323: Chapter 14 Digital I/O And Psl Configuration
CHAPTER 14 DIGITAL I/O AND PSL CONFIGURATION...
Page 324 Chapter 14 - Digital I/O and PSL Configuration P54A/B/C/E P54xMED-TM-EN-1...
Page 325: Chapter Overview
P54A/B/C/E Chapter 14 - Digital I/O and PSL Configuration CHAPTER OVERVIEW This chapter introduces the PSL (Programmable Scheme Logic) Editor, and describes the configuration of the digital inputs and outputs. It provides an outline of scheme logic concepts and the PSL Editor. This is followed by details about allocation of the digital inputs and outputs, which require the use of the PSL Editor.
Page 326: Configuring Digital Inputs And Outputs
Chapter 14 - Digital I/O and PSL Configuration P54A/B/C/E CONFIGURING DIGITAL INPUTS AND OUTPUTS Configuration of the digital inputs and outputs in this product is very flexible. You can use a combination of settings and programmable logic to customise them to your application. You can access some of the settings using the keypad on the front panel, but you will need a computer running the settings application software to fully interrogate and configure the properties of the digital inputs and outputs.
Page 327: Scheme Logic
P54A/B/C/E Chapter 14 - Digital I/O and PSL Configuration SCHEME LOGIC The product is supplied with pre-loaded Fixed Scheme Logic (FSL) and Programmable Scheme Logic (PSL). The Scheme Logic is a functional module within the IED, through which all mapping of inputs to outputs is handled. The scheme logic can be split into two parts;...
Page 328: Psl Editor
Chapter 14 - Digital I/O and PSL Configuration P54A/B/C/E PSL EDITOR The Programmable Scheme Logic (PSL) is a module of programmable logic gates and timers in the IED, which can be used to create customised logic to qualify how the product manages its response to system conditions. The IED's digital inputs are combined with internally generated digital signals using logic gates, timers, and conditioners.
Page 329: Configuring The Opto-Inputs
P54A/B/C/E Chapter 14 - Digital I/O and PSL Configuration CONFIGURING THE OPTO-INPUTS The number of optically isolated status inputs (opto-inputs) depends on the specific model supplied. The use of the inputs will depend on the application, and their allocation is defined in the programmable scheme logic (PSL). In addition to the PSL assignment, you also need to specify the expected input voltage.
Page 330: Assigning The Output Relays
Chapter 14 - Digital I/O and PSL Configuration P54A/B/C/E ASSIGNING THE OUTPUT RELAYS Relay contact action is controlled using the PSL. DDB signals are mapped in the PSL and drive the output relays. The driving of an output relay is controlled by means of a relay output conditioner. Several choices are available for how output relay contacts are conditioned.
Page 331: Fixed Function Leds
P54A/B/C/E Chapter 14 - Digital I/O and PSL Configuration FIXED FUNCTION LEDS Four fixed-function LEDs on the left-hand side of the front panel indicate the following conditions. Trip (Red) switches ON when the IED issues a trip signal. It is reset when the associated fault record is ●...
Page 332: Configuring Programmable Leds
Chapter 14 - Digital I/O and PSL Configuration P54A/B/C/E CONFIGURING PROGRAMMABLE LEDS There are three types of programmable LED signals which vary according to the model being used. These are: Single-colour programmable LED. These are red when illuminated. ● Tri-colour programmable LED. These can be illuminated red, green, or amber. ●...
Page 333 P54A/B/C/E Chapter 14 - Digital I/O and PSL Configuration Note: All LED DDB signals are always shown in the PSL Editor. However, the actual number of LEDs depends on the device hardware. For example, if a small 20TE device has only 4 programmable LEDs, LEDs 5-8 will not take effect even if they are mapped in the PSL.
Page 334: Function Keys
Chapter 14 - Digital I/O and PSL Configuration P54A/B/C/E FUNCTION KEYS For most models, a number of programmable function keys are available. This allows you to assign function keys to control functionality via the programmable scheme logic (PSL). Each function key is associated with a programmable tri-colour LED, which you can program to give the desired indication on activation of the function key.
Page 335: Control Inputs
P54A/B/C/E Chapter 14 - Digital I/O and PSL Configuration CONTROL INPUTS The control inputs are software switches, which can be set or reset locally or remotely. These inputs can be used to trigger any PSL function to which they are connected. There are three setting columns associated with the control inputs: CONTROL INPUTS, CTRL I/P CONFIG and CTRL I/P LABELS.
Page 336 Chapter 14 - Digital I/O and PSL Configuration P54A/B/C/E P54xMED-TM-EN-1...
Page 337: Chapter 15 Fibre Teleprotection
CHAPTER 15 FIBRE TELEPROTECTION...
Page 338 Chapter 15 - Fibre Teleprotection P54A/B/C/E P54xMED-TM-EN-1...
Page 339: Chapter Overview
P54A/B/C/E Chapter 15 - Fibre Teleprotection CHAPTER OVERVIEW This chapter provides information about the fibre-optic communication mechanism,which is used to provide unit schemes and general-purpose teleprotection signalling for protection of transmission lines and distribution feeders. The feature is called Fibre Teleprotection. This chapter contains the following sections: Chapter Overview Fibre Teleprotection Implementation...
Page 340: Fibre Teleprotection Implementation
Chapter 15 - Fibre Teleprotection P54A/B/C/E FIBRE TELEPROTECTION IMPLEMENTATION The Fibre Teleprotection interface is an integral part of the Current Differential protection implementation for this product. It provides the communications necessary for the Current Differential protection schemes as well as intertripping command signalling which can be freely allocated to realise protection schemes such as Permissive and Blocking schemes.
Page 341: Protection Communications Channel
C37.94 will be the only communication protocol for the protection communications for multi-ended line differential. 2Mbps E1 will be an additional communication protocol option that will be realised via GE recommended third party conversion box which will have C37.94 over fibre optic as an input and E1 at 2Mbps over copper as an output.
Page 342: Figure 156: Two Terminal Dual Channel Scheme
Chapter 15 - Fibre Teleprotection P54A/B/C/E Terminal 2 Data Terminal 1 Data Terminal 1 Terminal 2 Terminal 2 Data Terminal 1 Data E02525-2 Figure 156: Two terminal dual channel scheme Terminal 2 Terminal 3 Data Data Terminal 2 Terminal 1 Terminal 3 Terminal 1 Data...
Page 343: Figure 158: Four Terminal Scheme
P54A/B/C/E Chapter 15 - Fibre Teleprotection Terminal 2 Terminal 3 Terminal 4 Data Data Data Terminal 2 Terminal 1 Terminal 3 Terminal 4 Terminal 1 Data Data Data Terminal 3 Terminal 2 Terminal 1 Data Data Data Terminal 4 Terminal 3 Terminal 2 Terminal 1 Terminal 4...
Page 344: Figure 159: Five Terminal Scheme
Chapter 15 - Fibre Teleprotection P54A/B/C/E Terminal 2 Terminal 3 Terminal 4 Terminal 5 Data Data Data Data Terminal 2 Terminal 1 Terminal 3 Terminal 4 Terminal 5 Terminal 1 Data Data Data Data Terminal 5 Terminal 3 Terminal 4 E02525-5 Figure 159: Five terminal scheme P54xMED-TM-EN-1...
Page 345: Error Handling For Protection Communications
P54A/B/C/E Chapter 15 - Fibre Teleprotection Terminal 2 Terminal 3 Terminal 4 Terminal 5 Terminal 6 Data Data Data Data Data Terminal 2 Terminal 1 Terminal 3 Terminal 4 Terminal 5 Terminal 6 Terminal 1 Data Data Data Data Data Terminal 6 Terminal 3 Terminal 4...
Page 346: Fibre Teleprotection Scheme Terminal Addressing
Chapter 15 - Fibre Teleprotection P54A/B/C/E 3 to 6 ended If a single comms channel fails, or if a terminal is reconfigured out of service, comms can be re-routed the ● other way around the ring If 2 channels fails – No protection ●...
Page 347: Direct Connection
P54A/B/C/E Chapter 15 - Fibre Teleprotection Ch 1 1550 nm single-mode Not fitted 1550 nm single-mode 1550 nm single-mode 850 nm 1300 nm multi-mode 850 nm 1300 nm single-mode 850 nm 1550 nm single-mode 1300 nm multi-mode 850 nm 1300 nm single-mode 850 nm 1550 nm single-mode 850 nm...
Page 348: Communications Supervision
Chapter 15 - Fibre Teleprotection P54A/B/C/E COMMUNICATIONS SUPERVISION Since electrical power systems are generally required to operate continuously, it follows that the applied protection must do the same. If the protection uses communications, it must supervise these communications to take appropriate action should they become degraded or lost. IM64 provides the necessary communications supervision.
Page 349: Im64 Logic
P54A/B/C/E Chapter 15 - Fibre Teleprotection IM64 LOGIC Channel Timeout No Received Messages Ch 1 Ch1 Timeout Poor Channel Quality Ch 1 Signalling Fail Ch1 Degraded Channel Timeout No Received Messages Ch 2 Ch2 Timeout Poor Channel Quality Ch 2 Ch2 Degraded Scheme Setup &...
Page 350: Figure 163: Im64 Communications Mode And Ieee C37.94 Alarm Signals
Chapter 15 - Fibre Teleprotection P54A/B/C/E Channel 1 Communication Error in Receive Ch1 Signal Lost message (IEEE C37 .94) Message Info Error in Transit Ch1 Path Yellow Message Info Comms Mode Ch1 Mismatch RxN Channel Mismatch IEEE C37.94 IEEE C37 .94 Error in Receive Ch2 Signal Lost Message Info...
Page 351: Application Notes
P54A/B/C/E Chapter 15 - Fibre Teleprotection APPLICATION NOTES Effective communications are essential for the performance of teleprotection schemes. Disturbances on the communications links need to be detected and reported so that appropriate actions can be taken to ensure that the power system does not go unprotected. SCHEME RECONFIGURATION Each relay of the Multi-Ended Line Differential scheme has a reconfiguration feature.
Page 352: Two-Ended Scheme Extended Supervision
Chapter 15 - Fibre Teleprotection P54A/B/C/E The messages received on each channel are individually assessed for quality to ensure the IM64 signalling scheme is available for use. If no messages are received for a period equal to the Channel Timeout setting or the signal quality falls below a defined value, DDB signals are activated as shown in the IM64 channel fail and scheme fail logic diagram.
Page 353: Three-Ended Scheme Extended Supervision
P54A/B/C/E Chapter 15 - Fibre Teleprotection These inputs are user controls that indicate when the signalling is locally switched out of service Opto 1 Control Input 1 IM64 Ch1 output 8 Test Loopback IM64 Ch2 output 8 Test IM64 Non- &...
Page 354 Chapter 15 - Fibre Teleprotection P54A/B/C/E P54xMED-TM-EN-1...
Page 355: Chapter 16 Electrical Teleprotection
CHAPTER 16 ELECTRICAL TELEPROTECTION...
Page 356 Chapter 16 - Electrical Teleprotection P54A/B/C/E P54xMED-TM-EN-1...
Page 357: Chapter Overview
P54A/B/C/E Chapter 16 - Electrical Teleprotection CHAPTER OVERVIEW This chapter contains the following sections: Chapter Overview Introduction Teleprotection Scheme Principles Implementation Configuration Connecting to Electrical InterMiCOM Application Notes P54xMED-TM-EN-1...
Page 358: Introduction
Chapter 16 - Electrical Teleprotection P54A/B/C/E INTRODUCTION Electrical Teleprotection is an optional feature that uses communications links to create protection schemes. It can be used to replace hard wiring between dedicated relay output contacts and digital input circuits. Two products equipped with electrical teleprotection can connect and exchange commands using a communication link.
Page 359: Teleprotection Scheme Principles
P54A/B/C/E Chapter 16 - Electrical Teleprotection TELEPROTECTION SCHEME PRINCIPLES Teleprotection schemes use signalling to convey a trip command to remote circuit breakers to isolate circuits. Three types of teleprotection commands are commonly encountered: Direct Tripping ● Permissive Tripping ● Blocking Scheme ●...
Page 360: Implementation
Chapter 16 - Electrical Teleprotection P54A/B/C/E IMPLEMENTATION Electrical InterMiCOM is configured using a combination of settings in the INTERMICOM COMMS column, settings in the INTERMICOM CONF column, and the programmable scheme logic (PSL). The eight command signals are mapped to DDB signals within the product using the PSL. Signals being sent to a remote terminal are referenced in the PSL as IM Output 1 - IM Output 8.
Page 361: Configuration
P54A/B/C/E Chapter 16 - Electrical Teleprotection CONFIGURATION Electrical Teleprotection is compliant with IEC 60834-1:1999. For your application, you can customise individual command signals to the differing requirements of security, speed, and dependability as defined in this standard. You customise the command signals using the IM# Cmd Type cell in the INTERMICOM CONF column. Any command signal can be configured for: ●...
Page 362: Figure 166: Example Assignment Of Intermicom Signals Within The Psl
Chapter 16 - Electrical Teleprotection P54A/B/C/E E002521 Figure 166: Example assignment of InterMiCOM signals within the PSL Note: When an Electrical InterMiCOM signal is sent from a local terminal, only the remote terminal will react to the command. The local terminal will only react to commands initiated at the remote terminal. P54xMED-TM-EN-1...
Page 363: Connecting To Electrical Intermicom
P54A/B/C/E Chapter 16 - Electrical Teleprotection CONNECTING TO ELECTRICAL INTERMICOM Electrical InterMiCOM uses EIA(RS)232 communication presented on a 9-pin ‘D’ type connector. The connector is labelled SK5 and is located at the bottom of the 2nd Rear communication board. The port is configured as standard DTE (Data Terminating Equipment).
Page 364: Application Notes
Chapter 16 - Electrical Teleprotection P54A/B/C/E APPLICATION NOTES Electrical InterMiCOM settings are contained within two columns; INTERMICOM COMMS and INTERMICOM CONF. The INTERMICOM COMMS column contains all the settings needed to configure the communications, as well as the channel statistics and diagnostic facilities. The INTERMICOM CONF column sets the mode of each command signal and defines how they operate in case of signalling failure.
Page 365 P54A/B/C/E Chapter 16 - Electrical Teleprotection Note: As we have recommended Latched operation, the table does not contain recommendations for ‘Permissive’ mode. However, if you do select ‘Default’ mode, you should set IM# FrameSyncTim greater than those listed above. If you set IM# FrameSyncTim lower than the minimum setting listed above, the device could interpret a valid change in a message as a corrupted message.
Page 366 Chapter 16 - Electrical Teleprotection P54A/B/C/E P54xMED-TM-EN-1...
Page 367: Chapter 17 Communications
CHAPTER 17 COMMUNICATIONS...
Page 368 Chapter 17 - Communications P54A/B/C/E P54xMED-TM-EN-1...
Page 369: Chapter Overview
P54A/B/C/E Chapter 17 - Communications CHAPTER OVERVIEW This product supports Substation Automation System (SAS), and Supervisory Control and Data Acquisition (SCADA) communication. The support embraces the evolution of communications technologies that have taken place since microprocessor technologies were introduced into protection, control, and monitoring devices which are now ubiquitously known as Intelligent Electronic Devices for the substation (IEDs).
Page 370: Communication Interfaces
Chapter 17 - Communications P54A/B/C/E COMMUNICATION INTERFACES The products have a number of standard and optional communication interfaces. The standard and optional hardware and protocols are summarised below: Port Availability Physical layer Data Protocols Front Standard RS232 Local settings Courier Rear Port 1 SCADA Courier, MODBUS, IEC60870-5-103, DNP3.0...
Page 371: Serial Communication
P54A/B/C/E Chapter 17 - Communications SERIAL COMMUNICATION The physical layer standards that are used for serial communications for SCADA purposes are: EIA(RS)485 (often abbreviated to RS485) ● K-Bus (a proprietary customization of RS485) ● EIA(RS)232 is used for local communication with the IED (for transferring settings and downloading firmware updates).
Page 372: Eia(Rs)485 Biasing Requirements
Chapter 17 - Communications P54A/B/C/E 3.2.1 EIA(RS)485 BIASING REQUIREMENTS Biasing requires that the signal lines be weakly pulled to a defined voltage level of about 1 V. There should only be one bias point on the bus, which is best situated at the master connection point. The DC source used for the bias must be clean to prevent noise being injected.
Page 373: Figure 170: Remote Communication Using K-Bus
P54A/B/C/E Chapter 17 - Communications RS232 K-Bus Computer RS232-USB converter KITZ protocol converter V01001 Figure 170: Remote communication using K-Bus Note: An RS232-USB converter is only needed if the local computer does not provide an RS232 port. Further information about K-Bus is available in the publication R6509: K-Bus Interface Guide, which is available on request.
Page 374: Standard Ethernet Communication
Chapter 17 - Communications P54A/B/C/E STANDARD ETHERNET COMMUNICATION The type of Ethernet board depends on the chosen model. The available boards and their features are described in the Hardware Design chapter of this manual. The Ethernet interface is required for either IEC 61850 or DNP3 over Ethernet (protocol must be selected at time of order).
Page 375: Redundant Ethernet Communication
P54A/B/C/E Chapter 17 - Communications REDUNDANT ETHERNET COMMUNICATION Redundancy is required where a single point of failure cannot be tolerated. It is required in critical applications such as substation automation. Redundancy acts as an insurance policy, providing an alternative route if one route fails.
Page 376: Parallel Redundancy Protocol
Chapter 17 - Communications P54A/B/C/E PARALLEL REDUNDANCY PROTOCOL PRP (Parallel Reundancy Protocol) is defined in IEC 62439-3. PRP provides bumpless redundancy and meets the most demanding needs of substation automation. The PRP implementation of the REB is compatible with any standard PRP device.
Page 377: High-Availability Seamless Redundancy (Hsr)
P54A/B/C/E Chapter 17 - Communications HIGH-AVAILABILITY SEAMLESS REDUNDANCY (HSR) HSR is standardized in IEC 62439-3 (clause 5) for use in ring topology networks. Similar to PRP, HSR provides bumpless redundancy and meets the most demanding needs of substation automation. HSR has become the reference standard for ring-topology networks in the substation environment.
Page 378: Hsr Unicast Topology
Chapter 17 - Communications P54A/B/C/E 5.3.2 HSR UNICAST TOPOLOGY With unicast frames, there is just one destination and the frames are sent to that destination alone. All non- recipient devices simply pass the frames on. They do not process them in any way. In other words, D frames are produced only for the receiving DANH.
Page 379: Rapid Spanning Tree Protocol
P54A/B/C/E Chapter 17 - Communications T1000 switch PC SCADA DS Agile gateways Px4x Px4x Px4x Px4x Px4x Px4x Px4x Px4x Bay 1 Bay 2 Bay 3 E01066 Figure 174: HSR application in the substation RAPID SPANNING TREE PROTOCOL RSTP is a standard used to quickly reconnect a network fault by finding an alternative path. It stops network loops whilst enabling redundancy.
Page 380: Self Healing Protocol
Chapter 17 - Communications P54A/B/C/E SELF HEALING PROTOCOL The Self-Healing Protocol (SHP) implemented in the REB is a proprietary protocol that responds to the constraints of critical time applications such as the GOOSE messaging of IEC 61850. It is designed, primarily, to be used on PACiS Substation Automation Systems that employ the C264-SWR212 and/or H35x switches.
Page 381: Dual Homing Protocol
P54A/B/C/E Chapter 17 - Communications Primary Fibre Switch Switch Switch Rx (Ep) Tx (Ep) Tx (Es) Rx (Rs) Hx5x C264 Hx5x Secondary Fibre V01014 Figure 178: Redundant Ethernet ring architecture with IED, bay computer and Ethernet switches after failure DUAL HOMING PROTOCOL The Dual Homing Protocol (DHP) implemented in the REB is a proprietary protocol.
Page 382: Figure 179: Dual Homing Mechanism
Chapter 17 - Communications P54A/B/C/E Network 1 Network 2 Optical star Optical star Alstom Alstom H63x H63x Dual homing Dual homing Dual homing SWD21x SWD21x SWD21x Modified frames from network 1 Modified frames from network 2 No modified frames V01015 Figure 179: Dual homing mechanism The H36x is a repeater with a standard 802.3 Ethernet switch, plus the DHM.
Page 383: Configuring Ip Addresses
P54A/B/C/E Chapter 17 - Communications MiCOM H382 SCADA or PACiS OI DS Agile gateways H600 switch H600 switch Ethernet Up to 6 links C264 * Px4x ** C264 H368 Ethernet Up to 4 links RS485 Bay level Bay level Bay level Type 1 Type 2 Type 3...
Page 384: Configuring The Ied Ip Address
Chapter 17 - Communications P54A/B/C/E The switch IP address must be configured through the Ethernet network. Set by IED Configurator IED (IP1) AAA.BBB.CCC.DDD REB (IP2) WWW.XXX.YYY.ZZZ Set by Hardware Dip Switch SW 2 for SHP, DHP, or RSTP Set by PRP/HSR Configurator for PRP or HSR Set by Switch Manager for SHP and DHP Set by RSTP Configurator for RSTP Set by PRP /HSR Configurator for PRP or HSR...
Page 385 P54A/B/C/E Chapter 17 - Communications Warning: Configure the hardware settings before the device is installed. Refer to the safety section of the IED. Switch off the IED. Disconnect the power and all connections. Before removing the front cover, take precautions to prevent electrostatic discharge damage according to the ANSI/ESD-20.20 -2007 standard.
Page 386 Chapter 17 - Communications P54A/B/C/E Press the levers either side of the connector to disconnect the ribbon cable from the front panel. E01021 P54xMED-TM-EN-1...
Page 387: Prp/Hsr Configurator
P54A/B/C/E Chapter 17 - Communications Remove the redundant Ethernet board. Set the last octet of IP address using the DIP switches. The available range is 1 to 127. Example address 1 + 4 + 16 + 64 = 85 decimal 85 Unused SW2 Top view V01022...
Page 388: Installing The Configurator
Chapter 17 - Communications P54A/B/C/E RJ45 Ethernet switch Media Converter TXB RXB RXA TXA RXB TXB RXA TXA RXB TXB V01806 Figure 182: Connection using (a) an Ethernet switch and (b) a media converter 5.8.2 INSTALLING THE CONFIGURATOR To install the configurator: Double click the WinPcap installer.
Page 389: Prp/Hsr Device Identification
P54A/B/C/E Chapter 17 - Communications 5.8.4 PRP/HSR DEVICE IDENTIFICATION To configure the redundant Ethernet board, go to the main window and click the Identify Device button. A list of devices are shown with the following details: Device address ● MAC address ●...
Page 390: Hsr Configuration
Chapter 17 - Communications P54A/B/C/E The configurable parameters are as follows: Multicast Address: Use this field to configure the multicast destination address. All DANPs in the network ● must be configured to operate with the same multicast address for the purpose of network supervision. Node Forget Time: This is the time after which a node entry is cleared in the nodes table.
Page 391: End Of Session
P54A/B/C/E Chapter 17 - Communications PRP/HSR functionality. To add an entry in the forwarding database, click the Filtering Entries tab. Configure as follows: Select the Port Number and MAC Address Set the Entry type (Dynamic or Static) Set the cast type (Unicast or Multicast) Set theMGMT and Rate Limit Click the Create button.
Page 392: Installing The Configurator
Chapter 17 - Communications P54A/B/C/E RJ45 Ethernet switch Media Converter TX2 RX2 RX1 TX1 RX2 TX2 RX1 TX1 RX2 TX2 V01803 Figure 183: Connection using (a) an Ethernet switch and (b) a media converter 5.9.2 INSTALLING THE CONFIGURATOR To install the configurator: Double click the WinPcap installer.
Page 393: Rstp Ip Address Configuration
P54A/B/C/E Chapter 17 - Communications Note: Due to the time needed to establish the RSTP protocol, wait 25 seconds between connecting the PC to the IED and clicking the Identify Device button. The redundant Ethernet board connected to the PC is identified and its details are listed. Device address ●...
Page 394: End Of Session
Chapter 17 - Communications P54A/B/C/E Maximum value S.No Parameter Default value (second) Minimum value (second) (second) Bridge Max Age Bridge Hello Time Bridge Forward Delay Bridge Priority 32768 61440 5.9.8.1 BRIDGE PARAMETERS To read the RSTP bridge parameters from the board, From the main window click the device address to select the device.
Page 395: Installation
P54A/B/C/E Chapter 17 - Communications The Switch Manager tool is also intended for MiCOM Px4x IEDs with redundant Ethernet using Self Healing Protocol (SHP) and Dual Homing Protocol (DHP). This tool is used to identify IEDs and Alstom Switches, and to configure the redundancy IP address for the Alstom proprietary Self Healing Protocol and Dual Homing Protocol.
Page 396: Setup
Chapter 17 - Communications P54A/B/C/E 5.10.2 SETUP Make sure the PC has one Ethernet port connected to the Alstom switch. Configure the PC's Ethernet port on the same subnet as the Alstom switch. Select User or Admin mode. In User mode enter the user name as User, leave the password blank and click OK.
Page 397: Mirroring Function
P54A/B/C/E Chapter 17 - Communications 5.10.7 MIRRORING FUNCTION Port mirroring is a method of monitoring network traffic that forwards a copy of each incoming and outgoing packet from one port of the repeater to another port where the data can be studied. Port mirroring is managed locally and a network administrator uses it as a diagnostic tool.
Page 398: Simple Network Management Protocol (Snmp)
Chapter 17 - Communications P54A/B/C/E SIMPLE NETWORK MANAGEMENT PROTOCOL (SNMP) Simple Network Management Protocol (SNMP) is a network protocol designed to manage devices in an IP network. The MiCOM P40 Modular products can provide up to two SNMP interfaces on Ethernet models; one to the IED’s Main Processor for device level status information, and another directly to the redundant Ethernet board (where applicable) for specific Ethernet network level information.
Page 399: Redundant Ethernet Board Mib Structure
P54A/B/C/E Chapter 17 - Communications Address Name Trigger Trap? Date Time IRIG-B Status Battery Status Active Sync source SNTP Server 1 SNTP Server 2 SNTP Status PTP Status System Alarms Invalid Message Format Main Protection Fail Comms Changed Max Prop. Alarm 9-2 Sample Alarm 9-2LE Cfg Alarm Battery Fail...
Page 400 Chapter 17 - Communications P54A/B/C/E Address Name mgmt Mib-2 sysDescr sysUpTime sysName Remote Monitoring RMON statistics etherstat etherStatsEntry etherStatsUndersizePkts etherStatsOversizePkts etherStatsJabbers etherStatsCollisions etherStatsPkts64Octets etherStatsPkts65to127Octets etherStatsPkts128to255Octets etherStatsPkts256to511Octets etherStatsPkts512to1023Octets MIB structure for PRP/HSR Address Name Standard 62439 IECHighavailibility linkRedundancyEntityObjects lreConfiguration lreConfigurationGeneralGroup lreManufacturerName lreInterfaceCount lreConfigurationInterfaceGroup lreConfigurationInterfaces...
Page 401 P54A/B/C/E Chapter 17 - Communications Address Name lreMacAddressB lreAdapterAdminStateA lreAdapterAdminStateB lreLinkStatusA lreLinkStatusB lreDuplicateDiscard lreTransparentReception lreHsrLREMode lreSwitchingEndNode lreRedBoxIdentity lreSanA lreSanB lreEvaluateSupervision lreNodesTableClear lreProxyNodeTableClear lreStatistics lreStatisticsInterfaceGroup lreStatisticsInterfaces lreInterfaceStatsTable lreInterfaceStatsIndex lreCntTotalSentA lreCntTotalSentB lreCntErrWrongLANA lreCntErrWrongLANB lreCntReceivedA lreCntReceivedB lreCntErrorsA lreCntErrorsB lreCntNodes IreOwnRxCntA IreOwnRxCntB lreProxyNodeTable lreProxyNodeEntry reProxyNodeIndex reProxyNodeMacAddress Internet...
Page 402 Chapter 17 - Communications P54A/B/C/E Address Name sysName sysServices interfaces ifTable ifEntry ifIndex ifDescr ifType ifMtu ifSpeed ifPhysAddress ifAdminStatus ifOpenStatus ifLastChange ifInOctets ifInUcastPkts ifInNUcastPkts ifInDiscards ifInErrors ifInUnknownProtos ifOutOctets ifOutUcastPkts ifOutNUcastPkts ifOutDiscards ifOutErrors ifOutQLen ifSpecific rmon statistics etherStatsTable etherStatsEntry etherStatsIndex etherStatsDataSource etherStatsDropEvents etherStatsOctets etherStatsPkts...
Page 403: Accessing The Mib
P54A/B/C/E Chapter 17 - Communications Address Name etherStatsCollisions etherStatsPkts64Octets etherStatsPkts65to127Octets etherStatsPkts128to255Octets etherStatsPkts256to511Octets etherStatsPkts512to1023Octets etherStatsPkts1024to1518Octets etherStatsOwner etherStatsStatus ACCESSING THE MIB Various SNMP client software tools can be used. We recommend using an SNMP MIB browser, which can perform the basic SNMP operations such as GET, GETNEXT and RESPONSE. Note: There are two IP addresses visible when communicating with the Redundant Ethernet Card via the fibre optic ports: Use the one for the IED itself to the Main Processor SNMP interface, and use the one for the on-board Ethernet switch to access the...
Page 404 Chapter 17 - Communications P54A/B/C/E Authentication is used to check the identity of users, privacy allows for encryption of SNMP messages. Both are optional, however you must enable authentication in order to enable privacy. To configure these security options: If SNMPv3 has been enabled, set the Security Level setting. There are three levels; without authentication and without privacy (noAuthNoPriv), with authentication but without privacy (authNoPriv), and with authentication and with privacy (authPriv).
Page 405: Data Protocols
P54A/B/C/E Chapter 17 - Communications DATA PROTOCOLS The products supports a wide range of protocols to make them applicable to many industries and applications. The exact data protocols supported by a particular product depend on its chosen application, but the following table gives a list of the data protocols that are typically available.
Page 406: Courier Database
Chapter 17 - Communications P54A/B/C/E 7.1.2 COURIER DATABASE The Courier database is two-dimensional and resembles a table. Each cell in the database is referenced by a row and column address. Both the column and the row can take a range from 0 to 255 (0000 to FFFF Hexadecimal. Addresses in the database are specified as hexadecimal values, for example, 0A02 is column 0A row 02.
Page 407 P54A/B/C/E Chapter 17 - Communications 7.1.5.1 AUTOMATIC EVENT RECORD EXTRACTION This method is intended for continuous extraction of event and fault information as it is produced. It is only supported through the rear Courier port. When new event information is created, the Event bit is set in the Status byte. This indicates to the Master device that event information is available.
Page 408: Disturbance Record Extraction
Chapter 17 - Communications P54A/B/C/E The Menu Database contains tables of possible events, and shows how the contents of the above fields are interpreted. Fault and Maintenance records return a Courier Type 3 event, which contains the above fields plus two additional fields: ●...
Page 409: Courier Configuration
P54A/B/C/E Chapter 17 - Communications 7.1.9 COURIER CONFIGURATION To configure the device: Select the CONFIGURATION column and check that the Comms settings cell is set to Visible. Select the COMMUNICATIONS column. Move to the first cell down (RP1 protocol). This is a non-settable cell, which shows the chosen communication protocol –...
Page 410: Physical Connection And Link Layer
Chapter 17 - Communications P54A/B/C/E COMMUNICATIONS RP1 Port Config K-Bus If using EIA(RS)485, the next cell (RP1 Comms Mode) selects the communication mode. The choice is either IEC 60870 FT1.2 for normal operation with 11-bit modems, or 10-bit no parity. If using K-Bus this cell will not appear.
Page 411: Initialisation
P54A/B/C/E Chapter 17 - Communications If the optional fibre optic port is fitted, a menu item appears in which the active port can be selected. However the selection is only effective following the next power up. The IED address and baud rate can be selected using the front panel menu or by the settings application software. 7.2.2 INITIALISATION Whenever the device has been powered up, or if the communication parameters have been changed a reset...
Page 412: Test Mode
Chapter 17 - Communications P54A/B/C/E 7.2.8 TEST MODE It is possible to disable the device output contacts to allow secondary injection testing to be performed using either the front panel menu or the front serial port. The IEC 60870-5-103 standard interprets this as ‘test mode’. An event will be produced to indicate both entry to and exit from test mode.
Page 413: Dnp
P54A/B/C/E Chapter 17 - Communications COMMUNICATIONS RP1 Baud rate 9600 bits/s Move down to the next cell (RP1 Meas Period). The next cell down controls the period between IEC 60870-5-103 measurements. The IEC 60870-5-103 protocol allows the IED to supply measurements at regular intervals.
Page 414: Physical Connection And Link Layer
Chapter 17 - Communications P54A/B/C/E The DNP 3.0 protocol is defined and administered by the DNP Users Group. For further information on DNP 3.0 and the protocol specifications, please see the DNP website (www.dnp.org). 7.3.1 PHYSICAL CONNECTION AND LINK LAYER DNP 3.0 can be used with two physical layer protocols: EIA(RS)485, or Ethernet.
Page 415: Object 20 Binary Counters
P54A/B/C/E Chapter 17 - Communications DNP Latch DNP Latch DNP Latch DNP Latch Control Input (Latched) Aliased Control Input (Latched) Control Input (Pulsed ) Aliased Control Input (Pulsed ) The pulse width is equal to the duration of one protection iteration V01002 Figure 184: Control input behaviour Many of the IED’s functions are configurable so some of the Object 10 commands described in the following...
Page 416: Object 40 Analogue Output
Chapter 17 - Communications P54A/B/C/E Analogue values can be reported to the master station as primary, secondary or normalized values (which takes into account the IED’s CT and VT ratios), and this is settable in the COMMUNICATIONS column in the IED. Corresponding deadband settings can be displayed in terms of a primary, secondary or normalized value.
Page 417 P54A/B/C/E Chapter 17 - Communications DNP 3.0 Device Profile Document Models Covered: All models Highest DNP Level Supported*: For Requests: Level 2 *This is the highest DNP level FULLY supported. Parts of level 3 are For Responses: Level 2 also supported Device Function: Slave Notable objects, functions, and/or qualifiers supported in addition to the highest DNP levels supported (the complete list is described in the...
Page 418 Chapter 17 - Communications P54A/B/C/E DNP 3.0 Device Profile Document Direct Operate: Always Direct Operate - No Ack: Always Count > 1 Never Pulse On Always Pulse Off Sometimes Latch On Always Latch Off Always Queue Never Clear Queue Never Note: Paired Control points will accept Pulse On/Trip and Pulse On/Close, but only single point will accept the Pulse Off control command.
Page 419 P54A/B/C/E Chapter 17 - Communications Request Response Object (Library will parse) (Library will respond with) Function Codes (dec) Qualifier Codes Function Codes Qualifier Codes (hex) Object Variation Description (dec) Number Number (hex) Binary Input Change - Any (read) (no range, or all) Variation 07, 08 (limited qty)
Page 420 Chapter 17 - Communications P54A/B/C/E Request Response Object (Library will parse) (Library will respond with) Function Codes (dec) Qualifier Codes Function Codes Qualifier Codes (hex) Object Variation Description (dec) Number Number (hex) 16-Bit Frozen Counter without Flag 1 (read) 00, 01 (start-stop) 129 response 00, 01...
Page 421 P54A/B/C/E Chapter 17 - Communications Request Response Object (Library will parse) (Library will respond with) Function Codes (dec) Qualifier Codes Function Codes Qualifier Codes (hex) Object Variation Description (dec) Number Number (hex) Analog Input Deadband (Variation (read) 00, 01 (start-stop) 0 is used to request default (no range, or all) variation)
Page 422 Chapter 17 - Communications P54A/B/C/E Request Response Object (Library will parse) (Library will respond with) Function Codes (dec) Qualifier Codes Function Codes Qualifier Codes (hex) Object Variation Description (dec) Number Number (hex) (assign class) (no range, or all) File Event - Any Variation (read) (no range, or all) 07, 08...
Page 423 P54A/B/C/E Chapter 17 - Communications Indication Description Supported Set when data that has been configured as Class 1 data is ready to be sent to the master. Class 1 data available The master station should request this class data from the relay when this bit is set in a response.
Page 424: Dnp3 Configuration
Chapter 17 - Communications P54A/B/C/E Code Number Identifier Name Description Success The received request has been accepted, initiated, or queued. The request has not been accepted because the ‘operate’ message was received after the arm timer (Select Before Operate) timed out. Timeout The arm timer was started when the select operation for the same point was received.
Page 425: Iec 61850
P54A/B/C/E Chapter 17 - Communications COMMUNICATIONS RP1 Baud rate 9600 bits/s Move down to the next cell (RP1 Parity). This cell controls the parity format used in the data frames. The parity can be set to be one of None, Odd or Even. Make sure that the parity format selected on the IED is the same as that set on the master station.
Page 426: Benefits Of Iec 61850
Chapter 17 - Communications P54A/B/C/E There are two editions of IEC 61850; IEC 61850 edition 1 and IEC 61850 edition 2. The edition which this product supports depends on your exact model. 7.4.1 BENEFITS OF IEC 61850 The standard provides: Standardised models for IEDs and other equipment within the substation ●...
Page 427: Iec 61850 In Micom Ieds
P54A/B/C/E Chapter 17 - Communications Data Attributes stVal Data Objects Logical Nodes : 1 to n LN1: XCBR LN2: MMXU Logical Device : IEDs 1 to n Physical Device (network address) V01008 Figure 185: Data model layers in IEC 61850 The levels of this hierarchy can be described as follows: Data Frame format Layer...
Page 428: Iec 61850 Data Model Implementation
Chapter 17 - Communications P54A/B/C/E The IEC 61850 compatible interface standard provides capability for the following: Read access to measurements ● ● Refresh of all measurements at the rate of once per second. Generation of non-buffered reports on change of status or measurement ●...
Page 429: Ethernet Functionality
P54A/B/C/E Chapter 17 - Communications UINT16 ● UINT32 ● UINT8 ● 7.4.8.1 IEC 61850 GOOSE CONFIGURATION All GOOSE configuration is performed using the IEC 61850 Configurator tool available in the MiCOM S1 Agile software application. All GOOSE publishing configuration can be found under the GOOSE Publishing tab in the configuration editor window.
Page 430: Iec 61850 Edition 2
Chapter 17 - Communications P54A/B/C/E Any new configuration sent to the IED is automatically stored in the inactive configuration bank, therefore not immediately affecting the current configuration. Following an upgrade, the IEC 61850 Configurator tool can be used to transmit a command, which authorises activation of the new configuration contained in the inactive configuration bank.
Page 431: Figure 186: Edition 2 System - Backward Compatibility
P54A/B/C/E Chapter 17 - Communications V01056 Figure 186: Edition 2 system - backward compatibility An Edition 2 IED cannot normally operate within an Edition 1 IEC 61850 system. An Edition 2 IED can work for GOOSE messaging in a mixed system, providing the client is compatible with Edition 2. V01057 Figure 187: Edition 1 system - forward compatibility issues 7.4.11.2...
Page 432: Figure 188: Example Of Standby Ied
Chapter 17 - Communications P54A/B/C/E Currency setting group (CUG) ● Visible string setting (VSG) ● Curve shape setting (CSG) ● Of these, only ENS and ENC types are available from a MiCOM P40 IED when publishing GOOSE messages, so Data Objects using these Common Data Classes should not be published in mixed Edition 1 and Edition 2 systems.
Page 433: Figure 189: Standby Ied Activation Process
P54A/B/C/E Chapter 17 - Communications V01060 Figure 189: Standby IED Activation Process The following sequence would occur under this scenario: During the installation phase, a spare standby IED is installed in the substation. This can remain inactive, until it is needed to replace functions in one of several bays. The device is connected to the process bus, but does not have any subscriptions enabled.
Page 434: Read Only Mode
Chapter 17 - Communications P54A/B/C/E READ ONLY MODE With IEC 61850 and Ethernet/Internet communication capabilities, security has become an important issue. For this reason, all relevant General Electric IEDs have been adapted to comply with the latest cyber-security standards. In addition to this, a facility is provided which allows you to enable or disable the communication interfaces. This feature is available for products using Courier, IEC 60870-5-103, or IEC 61850.
Page 435: Iec 61850 Protocol Blocking
P54A/B/C/E Chapter 17 - Communications The following commands are still allowed: Read settings, statuses, measurands ● ● Read records (event, fault, disturbance) Time Synchronisation ● Change active setting group ● IEC 61850 PROTOCOL BLOCKING If Read-Only Mode is enabled for the Ethernet interfacing with IEC 61850, the following commands are blocked at the interface: All controls, including: ●...
Page 436: Time Synchronisation
Chapter 17 - Communications P54A/B/C/E TIME SYNCHRONISATION In modern protection schemes it is necessary to synchronise the IED's real time clock so that events from different devices can be time stamped and placed in chronological order. This is achieved in various ways depending on the chosen options and communication protocols.
Page 437: Irig-B Implementation
P54A/B/C/E Chapter 17 - Communications 9.1.1 IRIG-B IMPLEMENTATION Depending on the chosen hardware options, the product can be equipped with an IRIG-B input for time synchronisation purposes. The IRIG-B interface is implemented either on a dedicated card, or together with other communication functionality such as Ethernet.
Page 438: Ptp Domains
Chapter 17 - Communications P54A/B/C/E calculate delays. The main disadvantage is that more inaccuracy is introduced, because the method assumes that forward and reverse delays are always the same, which may not always be correct. When using end-to-end mode, the IED can be connected in a ring or line topology using RSTP or Self Healing Protocol without any additional Transparent Clocks.
Page 439: Chapter 18 Cyber-Security
CHAPTER 18 CYBER-SECURITY...
Page 440 Chapter 18 - Cyber-Security P54A/B/C/E P54xMED-TM-EN-1...
Page 441: Overview
P54A/B/C/E Chapter 18 - Cyber-Security OVERVIEW In the past, substation networks were traditionally isolated and the protocols and data formats used to transfer information between devices were often proprietary. For these reasons, the substation environment was very secure against cyber-attacks. The terms used for this inherent type of security are: Security by isolation (if the substation network is not connected to the outside world, it cannot be accessed ●...
Page 442: The Need For Cyber-Security
Chapter 18 - Cyber-Security P54A/B/C/E THE NEED FOR CYBER-SECURITY Cyber-security provides protection against unauthorised disclosure, transfer, modification, or destruction of information or information systems, whether accidental or intentional. To achieve this, there are several security requirements: Confidentiality (preventing unauthorised access to information) ●...
Page 443: Standards
P54A/B/C/E Chapter 18 - Cyber-Security STANDARDS There are several standards, which apply to substation cyber-security. The standards currently applicable to General Electric IEDs are NERC and IEEE1686. Standard Country Description NERC CIP (North American Electric Reliability Framework for the protection of the grid critical Cyber Assets Corporation) BDEW (German Association of Energy and Water Requirements for Secure Control and Telecommunication...
Page 444: Cip 002
Chapter 18 - Cyber-Security P54A/B/C/E 3.1.1 CIP 002 CIP 002 concerns itself with the identification of: Critical assets, such as overhead lines and transformers ● Critical cyber assets, such as IEDs that use routable protocols to communicate outside or inside the ●...
Page 445: Cip 007
P54A/B/C/E Chapter 18 - Cyber-Security Power utility responsibilities: General Electric's contribution: Provide physical security controls and perimeter monitoring. General Electric cannot provide additional help with this aspect. Ensure that people who have access to critical cyber assets don’t have criminal records. 3.1.6 CIP 007 CIP 007 covers the following points:...
Page 446 Chapter 18 - Cyber-Security P54A/B/C/E IED functions and features are assigned to different password levels. The assignment is fixed. ● The audit trail is recorded, listing events in the order in which they occur, held in a circular buffer. ● Records contain all defined fields from the standard and record all defined function event types where the ●...
Page 447: Cyber-Security Implementation
P54A/B/C/E Chapter 18 - Cyber-Security CYBER-SECURITY IMPLEMENTATION The General Electric IEDs have always been and will continue to be equipped with state-of-the-art security measures. Due to the ever-evolving communication technology and new threats to security, this requirement is not static. Hardware and software security measures are continuously being developed and implemented to mitigate the associated threats and risks.
Page 448: Four-Level Access
Chapter 18 - Cyber-Security P54A/B/C/E NERC compliant banner NERC Compliance NERC Compliance Warning Warning System Current Access Level Measurements System Voltage System Frequency Measurements System Power Plant Reference Measurements Description Date & Time V00403 Figure 192: Default display navigation FOUR-LEVEL ACCESS The menu structure contains four levels of access, three of which are password protected.
Page 449: Blank Passwords
P54A/B/C/E Chapter 18 - Cyber-Security Level Meaning Read Operation Write Operation All items writeable at level 1. Setting Cells that change visibility (Visible/Invisible). Setting Values (Primary/Secondary) selector Commands: Read All All data and settings are readable. Reset Indication Write Some Poll Measurements Reset Demand Reset Statistics...
Page 450: Access Level Ddbs
Chapter 18 - Cyber-Security P54A/B/C/E Passwords may or may not be NERC compliant ● Passwords may contain any ASCII character in the range ASCII code 33 (21 Hex) to ASCII code 122 (7A Hex) ● inclusive ● Only one password is required for all the IED interfaces 4.2.3 ACCESS LEVEL DDBS The 'Access level' cell is in the 'System data' column (address 00D0).
Page 451: Password Blocking
P54A/B/C/E Chapter 18 - Cyber-Security If the entered password is NERC compliant, the following text is displayed. NERC COMPLIANT P/WORD WAS SAVED If the password entered is not NERC-compliant, the user is required to actively confirm this, in which case the non- compliance is logged.
Page 452: Password Recovery
Chapter 18 - Cyber-Security P54A/B/C/E A similar response occurs if you try to enter the password through a communications port. The parameters can then be configured using the Attempts Limit, Attempts Timer and Blocking Timer settings in the SECURITY CONFIG column. Password blocking configuration Cell Setting...
Page 453: Password Encryption
P54A/B/C/E Chapter 18 - Cyber-Security The recovery password can be applied through any interface, local or remote. It will achieve the same result irrespective of which interface it is applied through. 4.4.2 PASSWORD ENCRYPTION The IED supports encryption for passwords entered remotely. The encryption key can be read from the IED through a specific cell available only through communication interfaces, not the front panel.
Page 454: Security Events Management
Chapter 18 - Cyber-Security P54A/B/C/E SECURITY EVENTS MANAGEMENT To implement NERC-compliant cyber-security, a range of Event records need to be generated. These log security issues such as the entry of a non-NERC-compliant password, or the selection of a non-NERC-compliant default display.
Page 455 P54A/B/C/E Chapter 18 - Cyber-Security Event Value Display PSL CONFG D/LOAD PSL CONFIG DOWNLOADED BY {int} GROUP {grp} SETTINGS D/LOAD SETTINGS DOWNLOADED BY {int} GROUP {grp} PSL STNG UPLOAD PSL SETTINGS UPLOADED BY {int} GROUP {grp} DNP STNG UPLOAD DNP SETTINGS UPLOADED BY {int} TRACE DAT UPLOAD TRACE DATA UPLOADED...
Page 456: Logging Out
Chapter 18 - Cyber-Security P54A/B/C/E LOGGING OUT If you have been configuring the IED, you should 'log out'. Do this by going up to the top of the menu tree. When you are at the Column Heading level and you press the Up button, you may be prompted to log out with the following display: DO YOU WANT TO LOG OUT?
Page 457: Chapter 19 Installation
CHAPTER 19 INSTALLATION...
Page 458 Chapter 19 - Installation P54A/B/C/E P54xMED-TM-EN-1...
Page 459: Chapter Overview
P54A/B/C/E Chapter 19 - Installation CHAPTER OVERVIEW This chapter provides information about installing the product. This chapter contains the following sections: Chapter Overview Handling the Goods Mounting the Device Cables and Connectors Case Dimensions P54xMED-TM-EN-1...
Page 460: Handling The Goods
Chapter 19 - Installation P54A/B/C/E HANDLING THE GOODS Our products are of robust construction but require careful treatment before installation on site. This section discusses the requirements for receiving and unpacking the goods, as well as associated considerations regarding product care and personal safety. Caution: Before lifting or moving the equipment you should be familiar with the Safety Information chapter of this manual.
Page 461: Mounting The Device
P54A/B/C/E Chapter 19 - Installation MOUNTING THE DEVICE The products are dispatched either individually or as part of a panel or rack assembly. Individual products are normally supplied with an outline diagram showing the dimensions for panel cut-outs and hole centres. The products are designed so the fixing holes in the mounting flanges are only accessible when the access covers are open.
Page 462: Rack Mounting
Chapter 19 - Installation P54A/B/C/E Caution: Do not fasten products with pop rivets because this makes them difficult to remove if repair becomes necessary. RACK MOUNTING Panel-mounted variants can also be rack mounted using single-tier rack frames (our part number FX0021 101), as shown in the figure below.
Page 463 P54A/B/C/E Chapter 19 - Installation Case size summation Blanking plate part number GJ2028 101 10TE GJ2028 102 15TE GJ2028 103 20TE GJ2028 104 25TE GJ2028 105 30TE GJ2028 106 35TE GJ2028 107 40TE GJ2028 108 P54xMED-TM-EN-1...
Page 464: Cables And Connectors
Chapter 19 - Installation P54A/B/C/E CABLES AND CONNECTORS This section describes the type of wiring and connections that should be used when installing the device. For pin- out details please refer to the Hardware Design chapter or the wiring diagrams. Caution: Before carrying out any work on the equipment you should be familiar with the Safety Section and the ratings on the equipment’s rating label.
Page 465: Power Supply Connections
P54A/B/C/E Chapter 19 - Installation POWER SUPPLY CONNECTIONS These should be wired with 1.5 mm PVC insulated multi-stranded copper wire terminated with M4 ring terminals. The wire should have a minimum voltage rating of 300 V RMS. Caution: Protect the auxiliary power supply wiring with a maximum 16 A high rupture capacity (HRC) type NIT or TIA fuse.
Page 466: Voltage Transformer Connections
Chapter 19 - Installation P54A/B/C/E VOLTAGE TRANSFORMER CONNECTIONS Voltage transformers should be wired with 2.5 mm PVC insulated multi-stranded copper wire terminated with M4 ring terminals. The wire should have a minimum voltage rating of 300 V RMS. WATCHDOG CONNECTIONS These should be wired with 1 mm PVC insulated multi-stranded copper wire terminated with M4 ring terminals.
Page 467: Ethernet Metallic Connections
P54A/B/C/E Chapter 19 - Installation 4.11 ETHERNET METALLIC CONNECTIONS If the device has a metallic Ethernet connection, it can be connected to either a 10Base-T or a 100Base-TX Ethernet hub. Due to noise sensitivity, we recommend this type of connection only for short distance connections, ideally where the products and hubs are in the same cubicle.
Page 468: Case Dimensions
Chapter 19 - Installation P54A/B/C/E CASE DIMENSIONS Not all products are available in all case sizes. CASE DIMENSIONS 40TE Sealing strip 8 off holes Dia. 3.4 155.40 23.30 177.0 159.00 (4U) 483 (19” rack) 181.30 10.35 202.00 Flush mouting panel A = Clearance holes Panel cut-out details B = Mouting holes...
Page 469: Case Dimensions 60Te
P54A/B/C/E Chapter 19 - Installation CASE DIMENSIONS 60TE E01409 Figure 197: 60TE case dimensions P54xMED-TM-EN-1...
Page 470: Case Dimensions 80Te
Chapter 19 - Installation P54A/B/C/E CASE DIMENSIONS 80TE E01410 Figure 198: 80TE case dimensions P54xMED-TM-EN-1...
Page 471: Chapter 20 Commissioning Instructions
CHAPTER 20 COMMISSIONING INSTRUCTIONS...
Page 472 Chapter 20 - Commissioning Instructions P54A/B/C/E P54xMED-TM-EN-1...
Page 473: Chapter Overview
P54A/B/C/E Chapter 20 - Commissioning Instructions CHAPTER OVERVIEW This chapter contains the following sections: Chapter Overview General Guidelines Commissioning Test Menu Commissioning Equipment Product Checks Electrical Intermicom Communication Loopback Intermicom 64 Communication Setting Checks IEC 61850 Edition 2 Testing Current Differential Protection Protection Timing Checks System Check and Check Synchronism Check Trip and Autoreclose Cycle...
Page 474: General Guidelines
Chapter 20 - Commissioning Instructions P54A/B/C/E GENERAL GUIDELINES General Electric IEDs are self-checking devices and will raise an alarm in the unlikely event of a failure. This is why the commissioning tests are less extensive than those for non-numeric electronic devices or electro-mechanical relays.
Page 475: Commissioning Test Menu
P54A/B/C/E Chapter 20 - Commissioning Instructions COMMISSIONING TEST MENU The IED provides several test facilities under the COMMISSION TESTS menu heading. There are menu cells that allow you to monitor the status of the opto-inputs, output relay contacts, internal Digital Data Bus (DDB) signals and user-programmable LEDs.
Page 476: Test Mode Cell
Chapter 20 - Commissioning Instructions P54A/B/C/E TEST MODE CELL This cell allows you to perform secondary injection testing. It also lets you test the output contacts directly by applying menu-controlled test signals. To go into test mode, select the Test Mode option in the Test Mode cell. This takes the IED out of service causing an alarm condition to be recorded and the Out of Service LED to illuminate.
Page 477: Static Test Mode
P54A/B/C/E Chapter 20 - Commissioning Instructions cycle. Once the trip output has operated the command text will revert to No Operation whilst the rest of the auto-reclose cycle is performed. To test subsequent three-phase autoreclose cycles, you repeat the Trip 3 Pole command.
Page 478: Im64 Test Pattern
Chapter 20 - Commissioning Instructions P54A/B/C/E 3.12 IM64 TEST PATTERN This cell is used with the IM64 Test Mode cell to set a 16-bit pattern (8 bits per channel), which is transmitted whenever the IM64 Test Mode cell is set to Enabled. The IM64 TestPattern cell has a binary string with one bit for each user-defined Inter-MiCOM command.
Page 479: Commissioning Equipment
P54A/B/C/E Chapter 20 - Commissioning Instructions COMMISSIONING EQUIPMENT Specialist test equipment is required to commission this product. We recognise three classes of equipment for commissioning : Recommended ● Essential ● Advisory ● Recommended equipment constitutes equipment that is both necessary, and sufficient, to verify correct performance of the principal protection functions.
Page 480: Advisory Test Equipment
Chapter 20 - Commissioning Instructions P54A/B/C/E Timer ● Test switches ● Suitable electrical test leads ● Continuity tester ● For products that use fibre-optic communications to implement unit protection schemes : Fibre optic test leads (minimum 2). 10m minimum length, multimode 50/125 µm or 62.5µm, OR single mode ●...
Page 481: Product Checks
P54A/B/C/E Chapter 20 - Commissioning Instructions PRODUCT CHECKS These product checks are designed to ensure that the device has not been physically damaged prior to commissioning, is functioning correctly and that all input quantity measurements are within the stated tolerances. If the application-specific settings have been applied to the IED prior to commissioning, you should make a copy of the settings.
Page 482: Visual Inspection
Chapter 20 - Commissioning Instructions P54A/B/C/E 5.1.1 VISUAL INSPECTION Warning: Check the rating information under the top access cover on the front of the IED. Warning: Check that the IED being tested is correct for the line or circuit. Warning: Record the circuit reference and system details.
Page 483: Watchdog Contacts
P54A/B/C/E Chapter 20 - Commissioning Instructions 5.1.5 WATCHDOG CONTACTS Using a continuity tester, check that the Watchdog contacts are in the following states: Terminals Contact state with product de-energised 11 - 12 on power supply board Closed 13 - 14 on power supply board Open 5.1.6 POWER SUPPLY...
Page 484: Test Lcd
Chapter 20 - Commissioning Instructions P54A/B/C/E Terminals Contact state with product energised 13 - 14 on power supply board Closed 5.2.2 TEST LCD The Liquid Crystal Display (LCD) is designed to operate in a wide range of substation ambient temperatures. For this purpose, the IEDs have an LCD Contrast setting.
Page 485: Test Leds
P54A/B/C/E Chapter 20 - Commissioning Instructions If the time and date is not being maintained by an IRIG-B signal, ensure that the IRIG-B Sync cell in the DATE AND TIME column is set to Disabled. Set the date and time to the correct local time and date using Date/Time cell or using the serial protocol. 5.2.4 TEST LEDS On power-up, all LEDs should first flash yellow.
Page 486: Test Serial Communication Port Rp1
Chapter 20 - Commissioning Instructions P54A/B/C/E Connect a continuity tester across the terminals corresponding to output relay 1 as shown in the external connection diagram. To operate the output relay set the Contact Test cell to Apply Test. Check the operation with the continuity tester. Measure the resistance of the contacts in the closed state.
Page 487: Test Serial Communication Port Rp2
P54A/B/C/E Chapter 20 - Commissioning Instructions is shown below. RS485 to RS232 would follow the same principle, only using a RS485-RS232 converter. Most modern laptops have USB ports, so it is likely you will also require a RS232 to USB converter too. RS232 K-Bus Computer...
Page 488: Test Ethernet Communication
Chapter 20 - Commissioning Instructions P54A/B/C/E 5.2.12 TEST ETHERNET COMMUNICATION For products that employ Ethernet communications, we recommend that testing be limited to a visual check that the correct ports are fitted and that there is no sign of physical damage. If there is no board fitted or the board is faulty, a NIC link alarm will be raised (providing this option has been set in the NIC Link Report cell in the COMMUNICATIONS column).
Page 489 P54A/B/C/E Chapter 20 - Commissioning Instructions Note: If a PC connected to the IED using the rear communications port is being used to display the measured current, the process will be similar. However, the setting of the Remote Values cell in the MEASURE’T SETUP column will determine whether the displayed values are in primary or secondary Amperes.
Page 490: Electrical Intermicom Communication Loopback
Chapter 20 - Commissioning Instructions P54A/B/C/E ELECTRICAL INTERMICOM COMMUNICATION LOOPBACK If the IED is used in a scheme with standard InterMiCOM communication (Electrical Teleprotection), you need to configure a loopback for testing purposes. SETTING UP THE LOOPBACK The communication path may include various connectors and signal converters before leaving the substation. We therefore advise making the loopback as close as possible to where the communication link leaves the substation.
Page 491: Intermicom Command Bits
P54A/B/C/E Chapter 20 - Commissioning Instructions 6.2.1 INTERMICOM COMMAND BITS To test the InterMiCOM command bits, go to the INTERMICOM COMMS column and do the following: Enter any test pattern in the Test Pattern cell in the by scrolling through and changing selected bits between 1 and 0.
Page 492: Intermicom 64 Communication
Chapter 20 - Commissioning Instructions P54A/B/C/E INTERMICOM 64 COMMUNICATION If the IED is used in a scheme with InterMiCOM communication, you need to configure a loopback for testing purposes. IM64 is fibre-based. Several different fibre-optic interfaces are available. In general, 1550 nm single-mode fibres, or 1300 nm single-mode or multimode fibres are used for direct connection.
Page 493: Loopback Test
P54A/B/C/E Chapter 20 - Commissioning Instructions Where direct fibre connections are used (or where multiplexer channels conforming to the IEEE C37.94 standard are used), connect an appropriate fibre-optic cable from the channel transmitter to the channel receiver port on the rear of the device. If the communications use P59x interface devices, connect the appropriate optical fibre(s) between the channel transmitter(s) on the IED used to make connection to the P59x optical receiver(s).
Page 494: Setting Checks
Chapter 20 - Commissioning Instructions P54A/B/C/E SETTING CHECKS The setting checks ensure that all of the application-specific settings (both the IED’s function and programmable scheme logic settings) have been correctly applied. Note: If applicable, the trip circuit should remain isolated during these checks to prevent accidental operation of the associated circuit breaker.
Page 495 P54A/B/C/E Chapter 20 - Commissioning Instructions For protection group settings and disturbance recorder settings, the changes must be confirmed before they are used. When all required changes have been entered, return to the column heading level and press the down cursor key. Before returning to the default display, the following prompt appears. Update settings? ENTER or CLEAR Press the Enter key to accept the new settings or press the Clear key to discard the new settings.
Page 496: Iec 61850 Edition 2 Testing
Chapter 20 - Commissioning Instructions P54A/B/C/E IEC 61850 EDITION 2 TESTING USING IEC 61850 EDITION 2 TEST MODES In a conventional substation, functionality typically resides in a single device. It is usually easy to physically isolate these functions, as the hardwired connects can simply be removed. Within a digital substation architecture however, functions may be distributed across many devices.
Page 497: Simulated Input Behaviour
P54A/B/C/E Chapter 20 - Commissioning Instructions SV Test Mode Setting Result Normal IED behaviour ● All sampled value data frames received with an IEC 61850 Test quality bit set ● are treated as invalid Disabled The IED will display the measurement values for sampled values with the ●...
Page 498: Test Procedure For Real Values
Chapter 20 - Commissioning Instructions P54A/B/C/E 9.3.1 TEST PROCEDURE FOR REAL VALUES This procedure is for testing with real values without operating plant. Set device into 'Contacts Blocked' Mode Select COMMISSION TESTS ® IED Test Mode ® Contacts Blocked Confirm new behaviour has been enabled View COMMISSION TESTS ®...
Page 499: Test Procedure For Simulated Values - With Plant
P54A/B/C/E Chapter 20 - Commissioning Instructions Set device into Simulation Listening Mode Select COMMISSION TESTS ® Subscriber Sim = Enabled If using sampled values set the sampled values test mode Select IEC 61850-9.2LE ® SV Test Mode ® Enabled Inject simulated signals using a test device connected to the Ethernet network. The device will continue to listen to ‘real’...
Page 500: Contact Test
Chapter 20 - Commissioning Instructions P54A/B/C/E The device will continue to listen to ‘real’ GOOSE messages until a simulated message is received. Once the simulated messages are received, the corresponding ‘real’ messages are ignored until the device is taken out of IED test mode. Each message is treated separately, but sampled values are considered as a single message.
Page 501: Current Differential Protection
P54A/B/C/E Chapter 20 - Commissioning Instructions CURRENT DIFFERENTIAL PROTECTION 10.1 CURRENT DIFFERENTIAL BIAS CHARACTERISTIC In the CONFIGURATION column, disable all protection elements other than the one being tested. Make a note of which elements need to be re-enabled after testing. Set the device to loopback mode, isolating it from the remote end.
Page 502: Upper Slope
Chapter 20 - Commissioning Instructions P54A/B/C/E Connection type Magnitude of differential current in phase B 3-terminal 0.333 x (Is1 + (1.5 x Ia x k1)) pu +/- 10 Assumption: Ia < Is2 Switch OFF the AC supply, read and clear all alarms. 10.1.2 UPPER SLOPE Repeat the lower slope test but with the bias current set in the A-phase to 3 pu.
Page 503 P54A/B/C/E Chapter 20 - Commissioning Instructions Phase B Reconfigure the test equipment to inject fault current into the B phase. Repeat the test, this time ensuring that the breaker trip contacts relative to B phase operation close correctly. Record the B phase trip time. Switch OFF the ac supply and reset the alarms Phase C Repeat the above procedure for the C phase.
Page 504: Protection Timing Checks
Chapter 20 - Commissioning Instructions P54A/B/C/E PROTECTION TIMING CHECKS There is no need to check every protection function. Only one protection function needs to be checked as the purpose is to verify the timing on the processor is functioning correctly. 11.1 DEPENDENCY CONDITIONS Some protection elements can be set to have dependencies on the availability of the protection communication...
Page 505: Performing The Test
P54A/B/C/E Chapter 20 - Commissioning Instructions Note: If the timer does not stop when the current is applied and stage 1 has been set for directional operation, the connections may be incorrect for the direction of operation set. Try again with the current connections reversed. 11.4 PERFORMING THE TEST Ensure that the timer is reset.
Page 506: System Check And Check Synchronism
Chapter 20 - Commissioning Instructions P54A/B/C/E SYSTEM CHECK AND CHECK SYNCHRONISM This function performs a comparison between the line voltage and the bus voltage. There are two voltage inputs to compare: one from the voltage transformer input from the line side of the circuit breaker (Main VT) ●...
Page 507: Check Trip And Autoreclose Cycle
P54A/B/C/E Chapter 20 - Commissioning Instructions CHECK TRIP AND AUTORECLOSE CYCLE If the auto-reclose function is being used, the circuit breaker trip and auto reclose cycle can be tested automatically by using the application-specific settings. To test the trip and close operation without operating the breaker, the following conditions must be satisfied: ●...
Page 508: End-To-End Communication Tests
Chapter 20 - Commissioning Instructions P54A/B/C/E END-TO-END COMMUNICATION TESTS If the IED is being used in a scheme with InterMiCOM communications you must perform end-to-end testing of the protection communications channels. In this section all loopbacks are removed and satisfactory communications between line ends of the IEDs in the scheme are confirmed.
Page 509: Restoring C37.94 Fibre Connections
P54A/B/C/E Chapter 20 - Commissioning Instructions 14.1.2 RESTORING C37.94 FIBRE CONNECTIONS When restoring C37.94 fibre connections, check the optical power level received from both the IED and the C37.94 multiplexer. Remove the loopback test fibres and at both ends of each channel used. Reconnect the fibre optic cables for communications between IEDs and the C37.94 compatible multiplexer.
Page 510: Onload Checks
Chapter 20 - Commissioning Instructions P54A/B/C/E ONLOAD CHECKS Warning: Onload checks are potentially very dangerous and may only be carried out by qualified and authorised personnel. Onload checks can only be carried out if there are no restrictions preventing the energisation of the plant, and the other devices in the group have already been commissioned.
Page 511: Measure Capacitive Charging Current
P54A/B/C/E Chapter 20 - Commissioning Instructions If the Local Values cell is set to Secondary, the values displayed should be equal to the applied secondary voltage. The values should be within 1% of the applied secondary voltages. However, an additional allowance must be made for the accuracy of the test equipment being used.
Page 512: Final Checks
Chapter 20 - Commissioning Instructions P54A/B/C/E FINAL CHECKS Remove all test leads and temporary shorting leads. If you have had to disconnect any of the external wiring in order to perform the wiring verification tests, replace all wiring, fuses and links in accordance with the relevant external connection or scheme diagram. The settings applied should be carefully checked against the required application-specific settings to ensure that they are correct, and have not been mistakenly altered during testing.
Page 513: Chapter 21 Maintenance And Troubleshooting
CHAPTER 21 MAINTENANCE AND TROUBLESHOOTING...
Page 514 Chapter 21 - Maintenance and Troubleshooting P54A/B/C/E P54xMED-TM-EN-1...
Page 515: Chapter Overview
P54A/B/C/E Chapter 21 - Maintenance and Troubleshooting CHAPTER OVERVIEW The Maintenance and Troubleshooting chapter provides details of how to maintain and troubleshoot products based on the Px4x and P40Agile platforms. Always follow the warning signs in this chapter. Failure to do so may result injury or defective equipment.
Page 516: Maintenance
Chapter 21 - Maintenance and Troubleshooting P54A/B/C/E MAINTENANCE MAINTENANCE CHECKS In view of the critical nature of the application, General Electric products should be checked at regular intervals to confirm they are operating correctly. General Electric products are designed for a life in excess of 20 years. The devices are self-supervising and so require less maintenance than earlier designs of protection devices.
Page 517: Replacing The Device
P54A/B/C/E Chapter 21 - Maintenance and Troubleshooting REPLACING THE DEVICE If your product should develop a fault while in service, depending on the nature of the fault, the watchdog contacts will change state and an alarm condition will be flagged. In the case of a fault, you can replace either the complete device or just the faulty PCB, identified by the in-built diagnostic software.
Page 518: Repairing The Device
Chapter 21 - Maintenance and Troubleshooting P54A/B/C/E Caution: If the top and bottom access covers have been removed, some more screws with smaller diameter heads are made accessible. Do NOT remove these screws, as they secure the front panel to the device. Note: There are four possible types of terminal block: RTD/CLIO input, heavy duty, medium duty, and MiDOS.
Page 519: Replacing Pcbs
P54A/B/C/E Chapter 21 - Maintenance and Troubleshooting Caution: Before removing the front panel, you should be familiar with the contents of the Safety Information section of this guide or the Safety Guide SFTY/4LM, as well as the ratings on the equipment’s rating label. To remove the front panel: Open the top and bottom access covers.
Page 520: Replacement Of Communications Boards
Chapter 21 - Maintenance and Troubleshooting P54A/B/C/E To replace the main processor board: Remove front panel. Place the front panel with the user interface face down and remove the six screws from the metallic screen, as shown in the figure below. Remove the metal plate. Remove the two screws either side of the rear of the battery compartment recess.
Page 521: Replacement Of The Input Module
P54A/B/C/E Chapter 21 - Maintenance and Troubleshooting Before fitting the replacement PCB check that the number on the round label next to the front edge of the PCB matches the slot number into which it will be fitted. If the slot number is missing or incorrect, write the correct slot number on the label.
Page 522: Replacement Of The I/O Boards
Chapter 21 - Maintenance and Troubleshooting P54A/B/C/E The power supply board is fastened to an output relay board with push fit nylon pillars. This doubled-up board is secured on the extreme left hand side, looking from the front of the unit. Remove front panel.
Page 523: Post Modification Tests
P54A/B/C/E Chapter 21 - Maintenance and Troubleshooting As part of the product's continuous self-monitoring, an alarm is given if the battery condition becomes poor. Nevertheless, you should change the battery periodically to ensure reliability. To replace the battery: Open the bottom access cover on the front of the relay. Gently remove the battery.
Page 524: Troubleshooting
Chapter 21 - Maintenance and Troubleshooting P54A/B/C/E TROUBLESHOOTING SELF-DIAGNOSTIC SOFTWARE The device includes several self-monitoring functions to check the operation of its hardware and software while in service. If there is a problem with the hardware or software, it should be able to detect and report the problem, and attempt to resolve the problem by performing a reboot.
Page 525: Out Of Service Led On At Power-Up
P54A/B/C/E Chapter 21 - Maintenance and Troubleshooting Test Check Action Error Code Identification These messages indicate that a problem has been detected on the IED’s The following text messages (in English) are displayed if a main processor board in the front panel. fundamental problem is detected, preventing the system from booting: Bus Fail –...
Page 526: Error Code During Operation
Chapter 21 - Maintenance and Troubleshooting P54A/B/C/E Test Check Action The VT type field in the model number is incorrect (no VTs fitted) ERROR CODE DURING OPERATION The IED performs continuous self-checking. If the IED detects an error it displays an error message, logs a maintenance record and after a short delay resets itself.
Page 527: Incorrect Analogue Signals
P54A/B/C/E Chapter 21 - Maintenance and Troubleshooting If the signal is correctly applied, this indicates failure of an opto-input, which may be situated on standalone opto- input board, or on an opto-input board that is part of the input module. Separate opto-input boards can simply be replaced.
Page 528: Ieee C37.94 Fail
Chapter 21 - Maintenance and Troubleshooting P54A/B/C/E 3.7.6 IEEE C37.94 FAIL This indicates a Signal Lost, a Path Yellow (indicating a fault on the communications channel) or a mismatch in the number of N*64 channels used on either channel 1 or channel 2. Further information can be found in the MEASUREMENTS 4 column.
Page 529 P54A/B/C/E Chapter 21 - Maintenance and Troubleshooting The local service contact provides the shipping information Your local service contact provides you with all the information needed to ship the product: Pricing details ○ ○ RMA number Repair centre address ○ If required, an acceptance of the quote must be delivered before going to the next stage.
Page 530 Chapter 21 - Maintenance and Troubleshooting P54A/B/C/E P54xMED-TM-EN-1...
Page 531: Chapter 22 Technical Specifications
CHAPTER 22 TECHNICAL SPECIFICATIONS...
Page 532 Chapter 22 - Technical Specifications P54A/B/C/E P54xMED-TM-EN-1...
Page 533: Chapter Overview
P54A/B/C/E Chapter 22 - Technical Specifications CHAPTER OVERVIEW This chapter describes the technical specifications of the product. This chapter contains the following sections: Chapter Overview Interfaces Protection Functions Monitoring, Control and Supervision Measurements and Recording Ratings Input / Output Connections Mechanical Specifications Type Tests Environmental Conditions...
Page 534: Interfaces
Chapter 22 - Technical Specifications P54A/B/C/E INTERFACES FRONT SERIAL PORT Front serial port (SK1) For local connection to laptop for configuration purposes Standard EIA(RS)232 Designation Connector 9 pin D-type female connector Isolation Isolation to ELV level Protocol Courier Constraints Maximum cable length 15 m DOWNLOAD/MONITOR PORT Front download port (SK2) For firmware downloads or monitor connection...
Page 535: Optional Rear Serial Port (Sk5)
P54A/B/C/E Chapter 22 - Technical Specifications REAR SERIAL PORT 2 Optional rear serial port (RP2) For SCADA communications (multi-drop) Standard EIA(RS)485, K-bus, EIA(RS)232 Designation Connector 9 pin D-type female connector Cable Screened twisted pair (STP) Supported Protocols Courier Isolation Isolation to SELV level Constraints Maximum cable length 1000 m for RS485 and K-bus, 15 m for RS232 OPTIONAL REAR SERIAL PORT (SK5)
Page 536: Rear Ethernet Port Copper
Chapter 22 - Technical Specifications P54A/B/C/E IRIG-B Interface (Modulated) Isolation Isolation to SELV level Constraints Maximum cable length 10 m Input signal peak to peak, 200 mV to 20 mV Input impedance 6 k ohm at 1000 Hz Accuracy < +/- 1 s per day REAR ETHERNET PORT COPPER Rear Ethernet port using CAT 5/6/7 wiring Main Use...
Page 537: 100 Base Fx Transmitter Characteristics
P54A/B/C/E Chapter 22 - Technical Specifications 2.10.2 100 BASE FX TRANSMITTER CHARACTERISTICS Parameter Min. Typ. Max. Unit Output Optical Power BOL 62.5/125 µm -16.8 dBm avg. NA = 0.275 Fibre EOL Output Optical Power BOL 50/125 µm -22.5 -20.3 dBm avg. NA = 0.20 Fibre EOL -23.5 Optical Extinction Ratio...
Page 538: Protection Functions
Chapter 22 - Technical Specifications P54A/B/C/E PROTECTION FUNCTIONS PHASE CURRENT DIFFERENTIAL PROTECTION Accuracy Pick-up Formula +/- 10% Drop-off 0.75 x Formula +/- 10% IDMT characteristic shape +/- 5% or 40 ms, whichever is greater DT operation +/- 2% or 20 ms, whichever is greater Typical instantaneous operation with default settings, back-to-back propagation delay included up to 4 terminals...
Page 539: Phase Overcurrent Directional Parameters
P54A/B/C/E Chapter 22 - Technical Specifications Accuracy IDMT operate +/-5% of expected operating time or 40 ms, whichever is greater* IEEE reset +/-5% or 40 ms, whichever is greater DT operate +/-2% of setting or 40 ms, whichever is greater DT reset Setting +/-5% Repeatability...
Page 540: Sensitive Earth Fault Protection
Chapter 22 - Technical Specifications P54A/B/C/E Negative Sequence Polarising accuracy Hysteresis <3° VN2> pick-up Setting+/-10% VN2> drop-off 0.9 x Setting +/-10% IN2> pick-up Setting+/-10% IN2> drop-off 0.9 x Setting +/-10% SENSITIVE EARTH FAULT PROTECTION IDMT pick-up 1.05 x Setting +/-5% DT Pick-up Setting +/- 5% Drop-off (IDMT + DT)
Page 541: Negative Sequence Overcurrent Protection
P54A/B/C/E Chapter 22 - Technical Specifications NEGATIVE SEQUENCE OVERCURRENT PROTECTION IDMT pick-up 1.05 x Setting +/-5% DT pick-up Setting +/- 5% Drop-off (IDMT and DT) 0.95 x Setting +/-5% IDMT operate +/- 5% or 40 ms, whichever is greater DT operate +/- 2% or 60 ms, whichever is greater DT Reset Setting +/- 5%...
Page 542: Monitoring, Control And Supervision
Chapter 22 - Technical Specifications P54A/B/C/E MONITORING, CONTROL AND SUPERVISION VOLTAGE TRANSFORMER SUPERVISION Fast block operation < 1 cycle Fast block reset < 1.5 cycles Time delay +/- 2% or 20 ms, whichever is greater STANDARD CURRENT TRANSFORMER SUPERVISION IN> Pick-up Setting +/- 5% VN<...
Page 543: Psl Timers
P54A/B/C/E Chapter 22 - Technical Specifications PSL TIMERS Output conditioner timer Setting +/- 2% or 50 ms, whichever is greater Dwell conditioner timer Setting +/- 2% or 50 ms, whichever is greater Pulse conditioner timer Setting +/- 2% or 50 ms, whichever is greater P54xMED-TM-EN-1...
Page 544: Measurements And Recording
Chapter 22 - Technical Specifications P54A/B/C/E MEASUREMENTS AND RECORDING GENERAL General Measurement Accuracy General measurement accuracy Typically +/- 1%, but +/- 0.5% between 0.2 - 2 In/Vn Phase 0° to 360° +/- 0.5% Current (0.05 to 3 In) +/- 1.0% of reading, or 4mA (1A input), or 20mA (5A input) Voltage (0.05 to 2 Vn) +/- 1.0% of reading Frequency (45 to 65 Hz)
Page 545: Ratings
P54A/B/C/E Chapter 22 - Technical Specifications RATINGS AC MEASURING INPUTS AC Measuring Inputs Nominal frequency 50 Hz or 60 Hz (settable) Operating range 45 to 65 Hz Phase rotation ABC or CBA CURRENT TRANSFORMER INPUTS AC Current Inputs Nominal current (In) 1A or 5A <...
Page 546: Nominal Burden
Chapter 22 - Technical Specifications P54A/B/C/E Cortec option (DC only) 19 to 65 V DC Cortec option (rated for AC or DC operation) 37 to 150 V DC Maximum operating range 32 to 110 V AC rms Cortec option (rated for AC or DC operation) 87 to 300 V DC 80 to 265 V AC rms Frequency range for AC supply...
Page 547: Battery Backup
P54A/B/C/E Chapter 22 - Technical Specifications Note: Maximum loading = all inputs/outputs energised. Note: Quiescent or 1/2 loading = 1/2 of all inputs/outputs energised. BATTERY BACKUP Location Front panel Type 1/2 AA, 3.6V Lithium Thionyly Chloride Battery reference LS14250 Lifetime >...
Page 548: Input / Output Connections
Chapter 22 - Technical Specifications P54A/B/C/E INPUT / OUTPUT CONNECTIONS ISOLATED DIGITAL INPUTS Opto-isolated digital inputs (opto-inputs) Compliance ESI 48-4 Rated nominal voltage 24 to 250 V dc Operating range 19 to 265 V dc Withstand 300 V dc Recognition time with half-cycle ac <...
Page 549: High Break Output Contacts
P54A/B/C/E Chapter 22 - Technical Specifications Make, carry and break, dc inductive 0.5 A for 1 s, 10000 operations (subject to the above limits) Make, carry and break ac resistive 30 A for 200 ms, 2000 operations (subject to the above limits) Make, carry and break ac inductive 10 A for 1.5 s, 10000 operations (subject to the above limits) Loaded contact...
Page 550: Mechanical Specifications
Chapter 22 - Technical Specifications P54A/B/C/E MECHANICAL SPECIFICATIONS PHYSICAL PARAMETERS 40TE Case Types* 60TE 80TE Weight (40TE case) 7 kg – 8 kg (depending on chosen options) Weight (60TE case) 9 kg – 12 kg (depending on chosen options) Weight (80TE case) 13 kg - 16 kg (depending on chosen options) Dimensions in mm (w x h x l) (40TE case) W: 206.0 mm H: 177.0 mm D: 243.1 mm...
Page 551: Type Tests
P54A/B/C/E Chapter 22 - Technical Specifications TYPE TESTS INSULATION Compliance IEC 60255-27: 2005 Insulation resistance > 100 M ohm at 500 V DC (Using only electronic/brushless insulation tester) CREEPAGE DISTANCES AND CLEARANCES Compliance IEC 60255-27: 2005 Pollution degree Overvoltage category Impulse test voltage (not RJ45) 5 kV Impulse test voltage (RJ45)
Page 552: Environmental Conditions
Chapter 22 - Technical Specifications P54A/B/C/E ENVIRONMENTAL CONDITIONS 10.1 AMBIENT TEMPERATURE RANGE Compliance IEC 60255-27: 2005 Test Method IEC 60068-2-1:2007 and IEC 60068-2-2 2007 Operating temperature range -25°C to +55°C (continuous) Storage and transit temperature range -25°C to +70°C (continuous) 10.2 TEMPERATURE ENDURANCE TEST Temperature Endurance Test...
Page 553: Electromagnetic Compatibility
P54A/B/C/E Chapter 22 - Technical Specifications ELECTROMAGNETIC COMPATIBILITY 11.1 1 MHZ BURST HIGH FREQUENCY DISTURBANCE TEST Compliance IEC 60255-22-1: 2008, Class III, IEC 60255-26:2013 Common-mode test voltage (level 3) 2.5 kV Differential test voltage (level 3) 1.0 kV 11.2 DAMPED OSCILLATORY TEST EN61000-4-18: 2011: Level 3, 100 kHz and 1 MHz.
Page 554: Surge Immunity Test
Chapter 22 - Technical Specifications P54A/B/C/E 11.6 SURGE IMMUNITY TEST Compliance IEC 61000-4-5: 2005 Level 4, IEC 60255-26:2013 Pulse duration Time to half-value: 1.2/50 µs Between all groups and protective earth conductor terminal Amplitude 4 kV Between terminals of each group (excluding communications ports, Amplitude 2 kV where applicable) 11.7...
Page 555: Magnetic Field Immunity
P54A/B/C/E Chapter 22 - Technical Specifications Test disturbance voltage 10 V rms Test using AM 1 kHz @ 80% Spot tests 27 MHz and 68 MHz 11.11 MAGNETIC FIELD IMMUNITY IEC 61000-4-8: 2009 Level 5 Compliance IEC 61000-4-9/10: 2001 Level 5 IEC 61000-4-8 test 100 A/m applied continuously, 1000 A/m applied for 3 s IEC 61000-4-9 test...
Page 556: Regulatory Compliance
Chapter 22 - Technical Specifications P54A/B/C/E REGULATORY COMPLIANCE Compliance with the European Commission Directive on EMC and LVD is demonstrated using a technical file. 12.1 EMC COMPLIANCE: 2014/30/EU The product specific Declaration of Conformity (DoC) lists the relevant harmonised standard(s) or conformit assessment used to demonstrate compliance with the EMC directive.
Page 557 P54A/B/C/E Chapter 22 - Technical Specifications Where: 'II' Equipment Group: Industrial. '(2)G' High protection equipment category, for control of equipment in gas atmospheres in Zone 1 and 2. This equipment (with parentheses marking around the zone number) is not itself suitable for operation within a potentially explosive atmosphere.
Page 558 Chapter 22 - Technical Specifications P54A/B/C/E P54xMED-TM-EN-1...
Page 559: Appendix A Ordering Options
APPENDIX A ORDERING OPTIONS...
Page 560 Appendix A - Ordering Options P54A/B/C/E P54xMED-TM-EN-1...
Page 561: Appendix B Settings And Signals
P54A/B/C/E Appendix A - Ordering Options Variants Order No. Current differential - 40TE with 3 pole only P54A Nominal auxiliary voltage 24-54 Vdc 48-125 Vdc (40-100 Vac) 110-250 Vdc (100-240 Vac) In/Vn rating In = 1A/5A ; Vn = 100-120Vac Hardware options Protocol Compatibilty Standard - None...
Page 562 Appendix A - Ordering Options P54A/B/C/E Variants Order No. Current differential - 40TE with 3 pole autoreclose and check synchronising (up to 6 ends application) P54B Nominal auxiliary voltage 24-54 Vdc 48-125 Vdc (40-100 Vac) 110-250 Vdc (100-240 Vac) In/Vn rating In = 1A/5A ;...
Page 563 P54A/B/C/E Appendix A - Ordering Options Variants Order No. Current differential - 60TE with 1/3 pole autoreclose and check synchronising (up to 6 ends application) P54C Nominal auxiliary voltage 24-54 Vdc 48-125 Vdc (40-100 Vac) 110-250 Vdc (100-240 Vac) In/Vn rating In = 1A/5A ;...
Page 564 Appendix A - Ordering Options P54A/B/C/E Variants Order No. Current differential - 80TE with 1/3 pole autoreclose and check synchronising (up to 6 ends application) P54E Nominal auxiliary voltage 24-54 Vdc 48-125 Vdc (40-100 Vac) 110-250 Vdc (100-240 Vac) In/Vn rating In = 1A/5A ;...
Page 565 APPENDIX B SETTINGS AND SIGNALS...
Page 566 Appendix B - Settings and Signals P54A/B/C/E P54xMED-TM-EN-1...
Page 567 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION SYSTEM DATA This column contains general system settings English Francais Language English Deutsch Espanol [Indexed String] Sets the required language to be used by the device 4 registers for writing 8 character password Each register contains a pair of characters Each register is formatted as follows:-...
Page 568 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION No Operation No Operation No Operation No Operation No Operation Trip CB2 Close CB2 [Indexed String] Supports trip and close commands if enabled in the Circuit Breaker Control menu. Visible to LCD+Front Port No Operation Trip Close...
Page 569 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IM64 Scheme Fail alarm IEEE C37.94 Communications Alarms Diff Protection inhibited Aid1 Channel Out Aid2 Channel Out Frequency out of range [Binary Flag (32) Indexed String] Displays the status of the first 32 alarms as a binary string.
Page 570 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION SR User Alarm 1 SR User Alarm 2 SR User Alarm 3 SR User Alarm 4 MR User Alarm 5 MR User Alarm 6 MR User Alarm 7 MR User Alarm 8 [Binary Flag (32) Indexed String]...
Page 571 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [ASCII Password (8)] Allows user to change password level 2. (8 characters) 4 registers for writing 8 character password Each register contains a pair of characters Each register is formatted as follows:- Password Level 3 AAAA...
Page 572 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Start C Start N Trip A Trip B Trip C Trip N [Binary Flag (8)] Displays the faulted phase. Started phases + tripped phases General Start Start I Diff Start Z1 Start Z2...
Page 573 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION I1 High V2 Low V2 High Z2 Low Z2 High Z3 Low Z3 High Z4 Low Z4 High Zp Low Zp High [Binary Flag (32) Indexed String] Displays the status of the second 32 start signals.
Page 574 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Trip I2>1 Trip V< 1 Trip V< 2 Trip V< A Trip V< B Trip V< C Trip V> 1 Trip V> 2 Trip V> A Trip V>...
Page 575 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Fault Location Fault Location [Courier Number (percentage)] Displays fault location in percentage. V1>1 Cmp Start V1>2 Cmp Start Start I>>Diff Start Elements 3 Start IN>NDiff StubBus Start [Binary Flag (32) Indexed String] Displays the status of the third 32 start signals.
Page 576 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [Courier Number (voltage)] Measured parameter VC Angle Pre Flt VC Angle Pre Flt [Courier Number (degrees)] Measured parameter VN Pre Flt VN Pre Flt [Courier Number (voltage)] Measured parameter VN Angle Pre Flt VN Angle Pre Flt...
Page 577 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION VN Fault VN Fault [Courier Number (voltage)] Measured parameter VN Angle Fault VN Angle Fault [Courier Number (degrees)] Measured parameter IA Local IA Local [Courier Number (current)] Measured parameter IB Local IB Local...
Page 578 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Measured parameter IA Differential IA Differential [Courier Number (current)] Measured parameter IB Differential IB Differential [Courier Number (current)] Measured parameter IC Differential IC Differential [Courier Number (current)] Measured parameter IA Bias IA Bias...
Page 579 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [Courier Number (current)] Measured parameter Fault IC Local Fault IC Local [Courier Number (current)] Measured parameter Fault IA rem 1 Fault IA rem 1 [Courier Number (current)] Measured parameter Fault IB rem 1 Fault IB rem 1...
Page 580 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Fault IA Bias Fault IA Bias [Courier Number (current)] Measured parameter Fault IB Bias Fault IB Bias [Courier Number (current)] Measured parameter Fault IC Bias Fault IC Bias [Courier Number (current)] Measured parameter From 0 to 9 in steps of 1...
Page 581 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IC Magnitude IC Phase Angle IC Phase Angle [Courier Number (angle)] IC Phase Angle IN Derived Mag IN Derived Mag [Courier Number (current)] IN Derived Mag IN Derived Angle IN Derived Angle [Courier Number (angle)]...
Page 582 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [Courier Number (voltage)] VBN Magnitude VBN Phase Angle VBN Phase Angle [Courier Number (angle)] VBN Phase Angle VCN Magnitude VCN Magnitude [Courier Number (voltage)] VCN Magnitude VCN Phase Angle VCN Phase Angle [Courier Number (angle)]...
Page 583 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION I1 Phase Angle I1 Phase Angle [Courier Number (angle)] I1 Phase Angle I2 Magnitude I2 Magnitude [Courier Number (current)] I2 Magnitude I2 Phase Angle I2 Phase Angle [Courier Number (angle)] I2 Phase Angle I0 Magnitude...
Page 584 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION A Phase VA A Phase VA [Courier Number (VA)] A Phase VA B Phase VA B Phase VA [Courier Number (VA)] B Phase VA C Phase VA C Phase VA [Courier Number (VA)] C Phase VA...
Page 585 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION 3 Phase Watts - Rolling Demand 3Ph VArs RollDem 3Ph VArs RollDem [Courier Number (VAr)] 3 Phase VArs - Rolling Demand IA Roll Demand IA Roll Demand [Courier Number (current)] IA Roll Demand IB Roll Demand...
Page 586 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IB remote 1 IB remote 1 [Courier Number (current)] IB remote 1 IC remote 1 IC remote 1 [Courier Number (current)] IC remote 1 IA remote 2 IA remote 2 [Courier Number (current)] IA remote 2...
Page 587 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION MEASUREMENTS 4 This column contains measurement parameters Ch 1 L-R1 Prop Dly Ch 1 L-R1 Prop Dly [Courier Number (time-seconds)] Channel 1 propagation time is displayed in seconds. These times are the ones calculated with asynchronous sampling (some times called “ping pong”...
Page 588 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION ITU- G8.21 and detailed in following cells Ch1 No.Errored s Ch1 No.Errored s [Unsigned Integer (32 bits)] Displays the number of seconds containing 1 or more errored or lost messages over channel 1 Ch1 No.Sev Err s Ch1 No.Sev Err s [Unsigned Integer (32 bits)]...
Page 589 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Channel 1 propagation time is displayed in seconds. These times are the ones calculated with asynchronous sampling (some times called “ping pong” method). Ch2 L-R5 PropDly Ch2 L-R5 PropDly [Courier Number (time-seconds)] Same as for channel 1...
Page 590 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [Indexed String] Reset the CB condition counters. I^ Maint Alarm I^ Lockout Alarm CB OPs Maint CB OPs Lock CB Time Maint CB Time Lockout Fault Freq Lock CB Monitoring I^ Maint Alarm I^ Lockout Alarm...
Page 591 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION If Rst CB mon LO by is set to CB close then CB mon LO RstDly timer allows reset of CB lockout state after set time delay No Operation In Service Autoreclose Mode...
Page 592 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION This command resets all CB shots counters to zero Disabled Res AROK by UI Enabled Enabled [Indexed String] If Enabled, this allows the successful auto-reclose signal to be reset by user interface command Reset AROK Ind. Disabled Res AROK by NoAR Disabled...
Page 593 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION None SNTP [Indexed String] Sets the primary time synchronisation source IRIG-B None Secondary Source None SNTP [Indexed String] Sets the secondary time synchronisation source From 0 to 127 in steps of 1 Domain Number [Integers] Assigns the PTP domain number.
Page 594 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [Courier Number (time-minutes)] Setting to specify an offset of -12 to +12 hrs in 15 minute intervals for local time zone. This adjustment is applied to the time based on the master clock which is UTC/GMT Disabled DST Enable...
Page 595 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION February March April June July August September October November December [Indexed String] Setting to specify the month in which daylight saving time adjustment ends From 0 to 1425 in steps of 15 DST End Mins [Courier Number (time-minutes)] Setting to specify the time of day in which daylight saving time adjustment ends.
Page 596 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Abort [Indexed String] Saves all IED settings. Group 1 Group 2 Copy From Group 1 Group 3 Group 4 [Indexed String] Allows displayed settings to be copied from a selected setting group No Operation Group 1 Group 2...
Page 597 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Enabled [Indexed String] To enable (activate) or disable (turn off) the back up Earth Fault Protection function. IN >stages: ANSI 50N/51N/67N Disabled Earth Fault Enabled Enabled [Indexed String] To enable (activate) or disable (turn off) the back up Earth Fault Protection function.
Page 598 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Invisible Record Control Visible Visible [Indexed String] Sets the Record Control menu visible further on in the IED settings menu. Invisible Disturb Recorder Visible Visible [Indexed String] Sets the Disturbance Recorder menu visible further on in the IED settings menu.
Page 599 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Enabled [Indexed String] Ethernet versions only. To enable (activate) or disable (turn off) Read Only Mode of Network Interface Card. From 0 to 31 in steps of 1 LCD Contrast [Indexed String] Sets the LCD contrast.
Page 600 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION To invert polarity (180 °) of the SEF CT Standard M CT Polarity Standard Inverted [Indexed String] To invert polarity (180 °) of the Mutual CT VT Connected [Indexed String] To indicate if voltage transformers are connected to the IED.
Page 601 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION repetitive recurrent changes such as an Opto input assigned for Minute Pulse clock synchronizing. High order word of long stored in 1st register DDB 63 - 32 0xFFFFFFFF Low order word of long stored in 2nd register [Binary Flag (32-Bit)]...
Page 602 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION High order word of long stored in 1st register DDB 447 - 416 0xFFFFFFFF Low order word of long stored in 2nd register [Binary Flag (32-Bit)] Chooses whether any individual DDB's should be deselected as a stored event, by setting the relevant bit to 0 (zero).
Page 603 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Low order word of long stored in 2nd register [Binary Flag (32-Bit)] Chooses whether any individual DDB's should be deselected as a stored event, by setting the relevant bit to 0 (zero). Typically used for repetitive recurrent changes such as an Opto input assigned for Minute Pulse clock synchronizing.
Page 604 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [Binary Flag (32-Bit)] Chooses whether any individual DDB's should be deselected as a stored event, by setting the relevant bit to 0 (zero). Typically used for repetitive recurrent changes such as an Opto input assigned for Minute Pulse clock synchronizing.
Page 605 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Chooses whether any individual DDB's should be deselected as a stored event, by setting the relevant bit to 0 (zero). Typically used for repetitive recurrent changes such as an Opto input assigned for Minute Pulse clock synchronizing. High order word of long stored in 1st register DDB 1631 - 1600 0xFFFFFFF1...
Page 606 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION repetitive recurrent changes such as an Opto input assigned for Minute Pulse clock synchronizing. High order word of long stored in 1st register DDB 2015 - 1984 0xFFFFFFFF Low order word of long stored in 2nd register [Binary Flag (32-Bit)]...
Page 607 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2)
Page 608 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly IN Sensitive V Checksync...
Page 609 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync Max Ih(2) IN Sensitive V Checksync IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2 VN Measured...
Page 610 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly...
Page 611 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IA Differential IB Differential IC Differential IN Differential Max I Bias Ch 1 Prop Delay Ch 2 Prop Delay IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync IN Sensitive V Checksync...
Page 612 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias...
Page 613 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync2 IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly VN Measured [Indexed String]...
Page 614 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync...
Page 615 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly IN Sensitive V Checksync V Checksync2 IA Differential IB Differential...
Page 616 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync P54xMED-TM-EN-1...
Page 617 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly...
Page 618 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Ch 2 Prop Delay IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive...
Page 619 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay...
Page 620 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly VN Measured [Indexed String] Selects any available analogue input to be assigned to this channel (including derived IN residual current). IA Differential IB Differential IC Differential...
Page 621 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential IB Differential...
Page 622 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync V Checksync2 IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly VN Measured...
Page 623 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2)
Page 624 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly IN Sensitive V Checksync...
Page 625 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync Max Ih(2) IN Sensitive V Checksync IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2 VN Measured...
Page 626 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly...
Page 627 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IA Differential IB Differential IC Differential IN Differential Max I Bias Ch 1 Prop Delay Ch 2 Prop Delay IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync IN Sensitive V Checksync...
Page 628 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias...
Page 629 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync2 IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly VN Measured [Indexed String]...
Page 630 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync...
Page 631 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly IN Sensitive V Checksync V Checksync2 IA Differential IB Differential...
Page 632 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync P54xMED-TM-EN-1...
Page 633 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly...
Page 634 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Ch 2 Prop Delay IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive...
Page 635 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay...
Page 636 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly VN Measured [Indexed String] Selects any available analogue input to be assigned to this channel (including derived IN residual current). IA Differential IB Differential IC Differential...
Page 637 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential IB Differential...
Page 638 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync V Checksync2 IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly VN Measured...
Page 639 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2)
Page 640 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly IN Sensitive V Checksync...
Page 641 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync Max Ih(2) IN Sensitive V Checksync IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2 VN Measured...
Page 642 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly...
Page 643 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IA Differential IB Differential IC Differential IN Differential Max I Bias Ch 1 Prop Delay Ch 2 Prop Delay IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync IN Sensitive V Checksync...
Page 644 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias...
Page 645 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync2 IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly VN Measured [Indexed String]...
Page 646 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Any of the digital channels may be selected to trigger the disturbance recorder on either a low to high or a high to low transition. From 0 to DDB Size in steps of 1 Digital Input 6 Relay 6 [Indexed String]...
Page 647 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Trigger L/H Trigger H/L [Indexed String] Any of the digital channels may be selected to trigger the disturbance recorder on either a low to high or a high to low transition. From 0 to DDB Size in steps of 1 Digital Input 13 Relay 13...
Page 648 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION The digital channels may monitor any of the opto isolated inputs or output contacts, in addition to a number of internal IED digital signals, such as protection starts, LEDs etc. No Trigger Trigger L/H Input 19 Trigger...
Page 649 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION From 0 to DDB Size in steps of 1 Digital Input 26 Opto Input 12 [Indexed String] The digital channels may monitor any of the opto isolated inputs or output contacts, in addition to a number of internal IED digital signals, such as protection starts, LEDs etc.
Page 650 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IC Differential IN Differential Max I Bias Ch 1 Prop Delay Ch 2 Prop Delay IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync IN Sensitive V Checksync Max Ih(2) IN Sensitive...
Page 651 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay...
Page 652 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly VN Measured [Indexed String] Selects any available analogue input to be assigned to this channel (including derived IN residual current).
Page 653 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential...
Page 654 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Ch 2 TX Prop Dly IN Sensitive V Checksync V Checksync2 IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly...
Page 655 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2)
Page 656 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly IN Sensitive V Checksync...
Page 657 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2...
Page 658 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly...
Page 659 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION VN Measured [Indexed String] Selects any available analogue input to be assigned to this channel (including derived IN residual current). IA Differential IB Differential IC Differential IN Differential Max I Bias Ch 1 Prop Delay...
Page 660 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias...
Page 661 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync V Checksync2 IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly VN Measured [Indexed String]...
Page 662 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync Max Ih(2) IN Sensitive V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2) VN Measured...
Page 663 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly IN Sensitive V Checksync...
Page 664 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync...
Page 665 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly...
Page 666 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IC Differential IN Differential Max I Bias Ch 1 Prop Delay Ch 2 Prop Delay IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync IN Sensitive V Checksync Max Ih(2) IN Sensitive...
Page 667 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay...
Page 668 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly VN Measured [Indexed String] Selects any available analogue input to be assigned to this channel (including derived IN residual current).
Page 669 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential...
Page 670 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Ch 2 TX Prop Dly IN Sensitive V Checksync V Checksync2 IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly...
Page 671 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2)
Page 672 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly IN Sensitive V Checksync...
Page 673 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2...
Page 674 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly...
Page 675 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION VN Measured [Indexed String] Selects any available analogue input to be assigned to this channel (including derived IN residual current). IA Differential IB Differential IC Differential IN Differential Max I Bias Ch 1 Prop Delay...
Page 676 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias...
Page 677 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync V Checksync2 IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly VN Measured [Indexed String]...
Page 678 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync Max Ih(2) IN Sensitive V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2) VN Measured...
Page 679 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly IN Sensitive V Checksync...
Page 680 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IN Sensitive V Checksync IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync...
Page 681 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly...
Page 682 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IC Differential IN Differential Max I Bias Ch 1 Prop Delay Ch 2 Prop Delay IN Sensitive V Checksync Max Ih(2) IN Sensitive V Checksync IN Sensitive V Checksync Max Ih(2) IN Sensitive...
Page 683 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay...
Page 684 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly VN Measured [Indexed String] Selects any available analogue input to be assigned to this channel (including derived IN residual current).
Page 685 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION V Checksync Max Ih(2) PLC Receive PLC Transmit IN Sensitive V Checksync V Checksync2 VN Measured IN Sensitive V Checksync V Checksync2 Max Ih(2) VN Measured IN Sensitive V Checksync IA Differential...
Page 686 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Ch 2 TX Prop Dly IN Sensitive V Checksync V Checksync2 IA Differential IB Differential IC Differential IN Differential Max I Bias Max Ih(2) Ch 1 Prop Delay Ch 2 Prop Delay Ch 1 TX Prop Dly Ch 2 TX Prop Dly...
Page 687 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Secondary [Indexed String] This setting controls whether measured values via the rear communication port are displayed as primary or secondary quantities. Measurement Ref [Indexed String] Using this setting the phase reference for all angular measurements by the IED can be selected. This reference is for Measurements 1. Measurements 3 uses always IA local as a reference Measurement Ref [Indexed String]...
Page 688 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION DNP3.0 versions only. Sets the address of Rear Port 1 From 1 to 30 in steps of 1 RP1 InactivTimer [Courier Number (time-minutes)] Defines the period of inactivity before IED reverts to its default state 9600 bits/s RP1 Baud Rate 19200 bits/s...
Page 689 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION 10-bit no parity [Indexed String] Courier versions only. The choice is either IEC 60870 FT1.2 for normal operation with 11-bit modems, or 10-bit no parity. 9600 bits/s 19200 bits/s RP1 Baud Rate 19200 bits/s...
Page 690 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION REAR PORT2 (RP2) RP2 versions only. Courier IEC870-5-103 RP2 Protocol Courier Modbus DNP 3.0 [Indexed String] RP2 versions only. Indicates the communications protocol that will be used on the rear communications port. Unsupported Card Not Fitted EIA232 OK...
Page 691 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Normalised Primary Meas Scaling Primary Secondary [Indexed String] DNP 3.0 over Ethernet versions only. Setting to report analogue values in terms of primary, secondary or normalized (with respect to the CT/VT ratio setting) values.
Page 692 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Trap destination 2 IP for the main processor SNMP version interface. This is set to the SNMP manager IP address. Setting this cell to 0.0.0.0 disables this Trap interface SNMPv3 Security SNMP v3 specific parameters heading.
Page 693 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION characters. The community name setting must be the same in both the SNMP Manager and the IED. COMMISSION TESTS This column contains commissioning test settings Opto I/P Status Opto I/P Status [Binary Flag (32) Indexed String] This menu cell displays the status of the available IED’s opto-isolated inputs as a binary string, a ‘1’...
Page 694 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION to be recorded and the yellow ‘Out of Service’ LED to illuminate. In IEC 60870-5-103 models it also changes the Cause of Transmission (COT) to Test Mode. In IED Test Mode, only control service commands from a client with a quality flat set to "test" will be processed as valid. To enable testing of output contacts the IED Test Mode cell should be set to Contacts Blocked.
Page 695 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Relay 13 Relay 14 Relay 15 Relay 16 Relay 17 Relay 18 Relay 19 Relay 20 Relay 21 Relay 22 Relay 23 Relay 24 Relay 25 Relay 26 Relay 27 Relay 28...
Page 696 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION been issued. Note: When the ‘Test Mode’ cell is set to ‘Enabled’ the ‘Relay O/P Status’ cell does not show the current status of the output relays and hence can not be used to confirm operation of the output relays.
Page 697 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [Binary Flag (32)] Displays the status of DDB signals DDB 95 - 64 DDB 95 - 64 [Binary Flag (32)] Displays the status of DDB signals DDB 127 - 96 DDB 127 - 96 [Binary Flag (32)]...
Page 698 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION DDB 703 - 672 DDB 703 - 672 [Binary Flag (32)] Displays the status of DDB signals DDB 735 - 704 DDB 735 - 704 [Binary Flag (32)] Displays the status of DDB signals DDB 767 - 736 DDB 767 - 736...
Page 699 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Displays the status of DDB signals DDB 1343 - 1312 DDB 1343 - 1312 [Binary Flag (32)] Displays the status of DDB signals DDB 1375 - 1344 DDB 1375 - 1344 [Binary Flag (32)] Displays the status of DDB signals...
Page 700 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION interrupter. This factor is set according to the type of Circuit Breaker used Alarm Disabled I^ Maintenance Alarm Disabled Alarm Enabled [Indexed String] Setting which determines if an alarm will be raised or not when the cumulative I^ maintenance counter threshold is exceeded. From 1 to 25000 in steps of 1 I^ Maintenance 1000...
Page 701 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION 24/27V 30/34V 48/54V Global Nominal V 24/27V 110/125V 220/250V Custom [Indexed String] Sets the nominal battery voltage for all opto inputs by selecting one of the five standard ratings in the Global Nominal V settings. If Custom is selected then each opto input can individually be set to a nominal voltage value.
Page 702 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [Indexed String] Each opto input can individually be set to a nominal voltage value if custom is selected for the global setting. The number of inputs may be up to 32, depending on the IED and I/O configuration.
Page 703 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION 48-54V 110-125V 220-250V [Indexed String] Each opto input can individually be set to a nominal voltage value if custom is selected for the global setting. The number of inputs may be up to 32, depending on the IED and I/O configuration.
Page 704 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION 24-27V 30-34V 48-54V Opto Input 23 24/27V 110-125V 220-250V [Indexed String] Each opto input can individually be set to a nominal voltage value if custom is selected for the global setting. The number of inputs may be up to 32, depending on the IED and I/O configuration.
Page 705 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Control Input 5 Control Input 6 Control Input 7 Control Input 8 Control Input 9 Control Input 10 Control Input 11 Control Input 12 Control Input 13 Control Input 14 Control Input 15 Control Input 16...
Page 706 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION No Operation Control Input 7 No Operation Reset [Indexed String] Setting to allow Control Inputs 7 set/ reset. No Operation Control Input 8 No Operation Reset [Indexed String] Setting to allow Control Inputs 8 set/ reset.
Page 707 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Reset [Indexed String] Setting to allow Control Inputs 19 set/ reset. No Operation Control Input 20 No Operation Reset [Indexed String] Setting to allow Control Inputs 20 set/ reset. No Operation Control Input 21 No Operation...
Page 708 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Reset [Indexed String] Setting to allow Control Inputs 31 set/ reset. No Operation Control Input 32 No Operation Reset [Indexed String] Setting to allow Control Inputs 32 set/ reset. CTRL I/P CONFIG This column contains settings for the type of control input (32 in all) From 0xFFFFFFFF to 32 in steps of 1...
Page 709 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Pulsed [Indexed String] Configures the control inputs as either ‘latched’ or ‘pulsed’. ON/OFF SET/RESET Ctrl Command 5 Set/Reset IN/OUT ENABLED/DISABLED [Indexed String] Allows the SET / RESET text, displayed in the hotkey menu, to be changed to something more suitable for the application of an individual control input, such as ON / OFF, IN / OUT etc.
Page 710 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION ENABLED/DISABLED [Indexed String] Allows the SET / RESET text, displayed in the hotkey menu, to be changed to something more suitable for the application of an individual control input, such as ON / OFF, IN / OUT etc.
Page 711 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [Indexed String] Configures the control inputs as either ‘latched’ or ‘pulsed’. ON/OFF SET/RESET Ctrl Command 16 Set/Reset IN/OUT ENABLED/DISABLED [Indexed String] Allows the SET / RESET text, displayed in the hotkey menu, to be changed to something more suitable for the application of an individual control input, such as ON / OFF, IN / OUT etc.
Page 712 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [Indexed String] Allows the SET / RESET text, displayed in the hotkey menu, to be changed to something more suitable for the application of an individual control input, such as ON / OFF, IN / OUT etc.
Page 713 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Configures the control inputs as either ‘latched’ or ‘pulsed’. ON/OFF SET/RESET Ctrl Command 27 Set/Reset IN/OUT ENABLED/DISABLED [Indexed String] Allows the SET / RESET text, displayed in the hotkey menu, to be changed to something more suitable for the application of an individual control input, such as ON / OFF, IN / OUT etc.
Page 714 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Allows the SET / RESET text, displayed in the hotkey menu, to be changed to something more suitable for the application of an individual control input, such as ON / OFF, IN / OUT etc. INTERMICOM COMMS This column is only visible if the model number supports InterMiCOM and second rear comms board is fitted.
Page 715 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Command that allows all Statistics and Channel Diagnostics to be reset. Invisible Ch Diagnostics Invisible Visible [Indexed String] Setting that makes visible or invisible Channel Diagnostics on the LCD. The diagnostic is reset by either IED’s powering down or using the ‘Reset Statistics’...
Page 716 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Allows specific bit statuses to be inserted directly into the InterMiCOM message, to substitute real data. This is used for testing purposes. Fail Loopback Status SCC Absent [Indexed String] Indicates the status of the InterMiCOM loopback mode OK = Loopback software (and hardware) is working correctly...
Page 717 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Setting that defines the operative mode of the InterMiCOM_3 signal. Selecting the channel response for this bit to Blocking allows fastest signalling, whereas setting to Direct offers higher security at the expense of speed.
Page 718 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Direct [Indexed String] Setting that defines the operative mode of the InterMiCOM_6 signal. Selecting the channel response for this bit to Blocking allows fastest signalling, whereas setting to Direct offers higher security at the expense of speed.
Page 719 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION FUNCTION KEYS This column contains the function key definitions Fn Key Status Fn Key Status [Binary Flag (10 bits) Indexed String] Displays the status of each function key. Disabled Unlocked (Enabled) Fn Key 1...
Page 720 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION remain ‘high’ as long as key is pressed. From 32 to 163 in steps of 1 Fn Key 4 Label Function Key 1 [ASCII Text (16 chars)] Allows the text of the function key to be changed to something more suitable for the application.
Page 721 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION From 32 to 163 in steps of 1 Fn Key 8 Label Function Key 1 [ASCII Text (16 chars)] Allows the text of the function key to be changed to something more suitable for the application. Disabled Unlocked (Enabled) Fn Key 9...
Page 722 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION only be set using the .MCL file. This setting allows for an Ethernet connection to be established with the relay without needing to first send a .MCL file via the serial port. Once a connection has been established the correct .MCL can be sent via Ethernet and this setting can be changed back to “Disabled”.
Page 723 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IEC 61850 versions only. The Publisher Sim cell allows the simulation bit to be sent in the GOOSE message, for example for testing or commissioning. When ‘Disabled’ is selected, the simulation bit for the goose control block is not set. When ‘Enabled’...
Page 724 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION From 0.1 to 600 in steps of 0.1s Comm Fail Timer [Courier Number (time-seconds)] Time delay after which the ‘Channel Fail Alarm’ will be issued providing that no messages were received during the ‘Channel Timeout’ period or the ‘Alarm Level’...
Page 725 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION From 0.05 to 0.95 in steps of 0.01 Alarm Level 0.25 [Courier Number (percentage)] This setting is the % of errored/lossed messages allowed before the Time out flag is set for the affected channel. This will also initiate the comm Fail timer.
Page 726 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Setting that defines the operative mode of the received InterMiCOM_4 signal. When ‘Direct’ tripping is chosen, for security reasons 2 consecutive valid messages have to be received before a change in the signal status will be acknowledged.
Page 727 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [Indexed String] Setting that defines the status of IM7 signal in case of heavy noise and message synchronization being lost. If set to Latching the last valid IM7 status will be maintained until the new valid message is received. If set to Default, the IM7 status, pre-defined by the user in IM7 Default Value cell will be set.
Page 728 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION ERROR_RATE_100% [Indexed String] Tdiscrim In order to avoid post trip mute of PLC during single pole opening, a discrimination timer can be set to avoid tripping for external faults following a single phase internal fault.
Page 729 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION The password level adopted by the IED after an inactivity timeout, or after the user logs out. This will be either the level of the highest level password that is blank, or level 0 if no passwords are blank.
Page 730 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [ASCII Text (16 chars)] Text label to describe each individual control input. This text is displayed when a control input is accessed by the hotkey menu. It is displayed in the programmable scheme logic description of the control input From 32 to 163 in steps of 1 Control Input 15...
Page 731 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [ASCII Text (16 chars)] Text label to describe each individual control input. This text is displayed when a control input is accessed by the hotkey menu. It is displayed in the programmable scheme logic description of the control input From 32 to 163 in steps of 1 Control Input 30...
Page 732 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION kZm = ZM0/3Z1 Angle setting kZm is visible if ‘Mutual Comp’ is enabled. This setting is a used for fault locator and Distance protection (when set to simple mode) .
Page 733 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION T6 J3 T1 J4 T2 J4 T3 J4 T4 J4 T5 J4 T6 J4 [Binary Flag (24) & Indexed String] A map of the terminals and junctions in the system for P541 only From 100 to 10000000 in steps of 10 Length Local 45000...
Page 734 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION they will be deduced via fomular From 0.05*v1/I1 to 500*V1/I1 in steps of 0.01*V1/I1 Z1 J1-J2 [Courier Number (impedance)] Positive sequence impedance amplitude between J1 and J2 From 0 to 10 in steps of 0.1 Z1 angle J1-J2 [Courier Number (angle)]...
Page 735 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Zero sequence impedance angle of the section between J3 and J4 From 0.00000001*I1 to 10*I1 in steps of Y1 J3-J4 0.00000001*I1 0.00000001*I1 [Courier Number (inverse ohms)] Positive sequence admittance amplitude of the section between junction J3 and J4 From 0.00000001*I1 to 10*I1 in steps of Y0 J3-J4...
Page 736 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION If Ph Diff Stub Bus is enabled, DDB input signal Stub Bus Enabled is energised and phase current is measured above Ph Is1 Stub Bus setting, the IED will issue a Stub Bus Trip From 0.1*l1 to 12*l1 in steps of 0.01*l1 Ph Is1 StubBus...
Page 737 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION En VTSorCh Fail En VTSandCh Fail [Indexed String] Setting that defines first stage overcurrent operating status. Depending on this setting, I>1 will be enabled permanently or in case of Voltage Transformer Supervision (fuse fail) operation, or in case of communication channel fail, or a combination (and /or) of both.
Page 738 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION En VTSorCh Fail En VTSandCh Fail [Indexed String] Setting that defines second stage overcurrent operating status. Depending on this setting, I>2 will be enabled permanently or in case of Voltage Transformer Supervision (fuse fail) operation, or in case of communication channel fail, or a combination (and /or) of both.
Page 739 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION En VTSorCh Fail En VTSandCh Fail [Indexed String] Setting that defines third stage overcurrent operating status. Depending on this setting, I>3 will be enabled permanently or in case of Voltage Transformer Supervision (fuse fail) operation, or in case of communication channel fail, or a combination (and /or) of both.
Page 740 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Default Curve 2 Default Curve 3 Default Curve 4 [Indexed String] Setting to determine the type of reset/release characteristic of the User defined curves. Default Curve 1 Default Curve 2 I>2 Usr Rst Char Default Curve 3...
Page 741 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IEC E Inverse UK LT Inverse IEEE M Inverse IEEE V Inverse IEEE E Inverse US Inverse US ST Inverse [Indexed String] Setting for the tripping characteristic for the second stage negative sequence overcurrent element. Non-Directional Directional Fwd I2>2 Directional...
Page 742 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION From 0 to 100 in steps of 0.01 I2>4 Time Delay [Courier Number (time-seconds)] Setting for the operating time-delay for the fourth stage negative sequence overcurrent element. VTS Blocks I2>1 VTS Blocks I2>2 I2>...
Page 743 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Default Curve 2 Default Curve 3 Default Curve 4 [Indexed String] Setting for the tripping characteristic for the first stage earth fault overcurrent element. Non-Directional Directional Fwd IN>1 Directional Non-Directional Directional Rev...
Page 744 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION UK LT Inverse IEEE M Inverse IEEE V Inverse IEEE E Inverse US Inverse US ST Inverse Default Curve 1 Default Curve 2 Default Curve 3 Default Curve 4 [Indexed String] Setting for the tripping characteristic for the second stage earth fault overcurrent element.
Page 745 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION En VTSandCh Fail [Indexed String] Setting that defines third stage overcurrent operating status. Depending of this setting, IN>3 will be enabled permanently or in case of Voltage Transformer Supervision (fuse fail) operation, or in case of communication channel fail, or a combination (and /or) of both.
Page 746 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Neg Sequence [Indexed String] Setting that determines whether the directional function uses zero sequence or negative sequence voltage polarizing. Measured IN> VNpol Input Derived Derived [Indexed String] Setting determines which will be selected as the input source of polarizing voltage for directional decision, 'derived' or 'measured'.
Page 747 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Directional Fwd Directional Rev [Indexed String] This setting determines the direction of measurement for the first stage sensitive earth fault element. From 0.005*I3 to 0.1*I3 in steps of 0.00025*I3 ISEF>1 Current 0.05 [Courier Number (current)]...
Page 748 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [Courier Number (time-seconds)] Setting for the time delay for the second stage definite time element. From 0.025 to 1.2 in steps of 0.005 ISEF>2 TMS [Courier Number (decimal)] Setting for the time multiplier to adjust the operating time of the IEC IDMT characteristic.
Page 749 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION From -95 to 95 in steps of 1 ISEF> Char Angle [Courier Number (angle)] Setting for the IED characteristic angle used for the directional decision. Measured ISEF>VNpol Input Derived Derived...
Page 750 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION From 0 to 100 in steps of 0.01 VN>1 tReset [Courier Number (time-seconds)] Setting to determine the reset/release definite time for the first stage characteristic Disabled VN>2 Status Disabled Enabled...
Page 751 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION From 10*V1 to 120*V1 in steps of 1*V1 V<1 Voltage Set [Courier Number (voltage)] Sets the pick-up setting for first stage undervoltage element. From 0 to 100 in steps of 0.01 V<1 Time Delay [Courier Number (time-seconds)] Setting for the operating time-delay for the first stage definite time undervoltage element.
Page 752 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION From 0.5 to 100 in steps of 0.5 V>1 TMS [Courier Number (decimal)] Setting for the time multiplier setting to adjust the operating time of the IDMT characteristic. Disabled V>2 Status Disabled...
Page 753 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Setting that determines the pick-up threshold for the second stage underfrequency element. From 0 to 100 in steps of 0.01 F<2 Time Delay [Courier Number (time-seconds)] Setting that determines the minimum operating time-delay for the second stage underfrequency element.
Page 754 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Enabled [Indexed String] Setting to enable or disable the first stage df/dt element. From 0.1 to 10 in steps of 0.1 df/dt>1 Setting [Courier Number (Hz/sec)] Pick-up setting for the first stage df/dt element.
Page 755 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION From 0 to 100 in steps of 0.01 df/dt>4 Time [Courier Number (time-seconds)] Minimum operating time-delay setting for the fourth stage df/dt element. GROUP 1: CB FAIL & P.DEAD This column contains settings for Circuit Fail and Under Current BREAKER FAIL...
Page 756 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION I< Only CB Open & I< Prot Reset & I< CB1 Ext Prot Rst Prot Reset & I< Prot Reset or I< Rst or CBOp & I< [Indexed String] Setting which determines the elements that will reset the circuit breaker fail time for external protection function initiated circuit breaker fail conditions.
Page 757 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [Courier Number (time-seconds)] Setting that determines the operating time-delay of the element upon detection of a voltage supervision condition. From 0.08*I1 to 32*I1 in steps of 0.01*I1 VTS I>...
Page 758 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [Indexed String] This setting determines whether the following operations will occur upon detection of CTS. • CTS set to provide alarm indication only. • CTS set to restrain local protection Note: The setting applies to both CTS algorithms.
Page 759 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Bus is considered Live with voltage above this setting. From 5 to 132 in steps of 0.5 Live Bus 1 [Courier Number (voltage)] Bus 1 is considered Live with voltage above this setting. From 5 to 132 in steps of 0.5 Dead Bus [Courier Number (voltage)]...
Page 760 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION From 0 to 90 in steps of 1 CS1 Angle [Courier Number (angle)] Maximum permitted phase angle between Line and Bus 1 voltages for first stage synchronism check element to reclose CB. From 0 to 90 in steps of 1 CB1 CS1 Angle [Courier Number (angle)]...
Page 761 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION bus voltages (refer to setting CS2 Slip Freq) Disabled CB1 CS2 SlipCtrl Enabled Enabled [Indexed String] Setting to enable or disable blocking of synchronism check stage 2 for reclosing CB1 by excessive frequency difference (slip) between line and bus voltages (refer to setting CB1 CS2 SlipFreq) From 0.005 to 2 in steps of 0.005 CS2 Slip Freq...
Page 762 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [Indexed String] This setting enables CB1 to close by manual control when the system satisfies all the System Check Synchronism Stage 2 conditions as listed under the setting CS2 Status in the SYSTEM CHECKS column. Disabled CB1M SC CS2 Disabled...
Page 763 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION AR 3P AR Opto [Indexed String] This setting determines which auto-reclose modes are permitted for the circuit breaker : single phase (AR 1P) only, both single phase and three phase (AR 1/3P), three phase only (AR 3P), or the auto-reclosing mode is controlled by opto input signals (AR Opto) mapped via DDB's (1497) AR Mode 1P and (1498) AR Mode 3P.
Page 764 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION If set to “Enable”, allows the first programmed reclose attempt (“shot”) to be omitted if the “Skip Shot 1” input is high when the Increment is triggered at the start of an autoreclose cycle: Allow Autoclose BAR 2 and 3Ph...
Page 765 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION From 0 to 10 in steps of 0.01 SP AR Dead Time [Courier Number (time-seconds)] Dead time setting for single phase auto-reclose. From 0.01 to 300 in steps of 0.01 3P AR DT Shot 1 [Courier Number (time-seconds)] Dead time setting for three phase auto-reclose (first shot).
Page 766 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Initiate AR Dir Aided AR Block AR Block AR [Indexed String] Setting that determines impact of aided Directional Comparison protection (DEF) on AR operation. (Only in models with distance option) Initiate AR TOR AR Block AR...
Page 767 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Setting that determines impact of the second stage sensitive earth fault overcurrent protection on AR operation. No Action Initiate AR ISEF>3 AR No Action Block AR [Indexed String] Setting that determines impact of the third stage sensitive earth fault overcurrent protection on AR operation.
Page 768 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION This setting enables CB1 to auto-reclose as leader when the system satisfies all the System Check Synchronism Stage 1 criteria as defined under CB1 CS1 Status settings in the SYSTEM CHECKS column. Disabled CB SC CS2 Disabled...
Page 769 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [ASCII Text (16 chars)] Label for Opto Input 4 From 32 to 163 in steps of 1 Opto Input 5 Input L5 [ASCII Text (16 chars)] Label for Opto Input 5 From 32 to 163 in steps of 1 Opto Input 6...
Page 770 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION From 32 to 163 in steps of 1 Opto Input 24 Input L24 [ASCII Text (16 chars)] Label for Opto Input 24 From 32 to 163 in steps of 1 Opto Input 25 Input L25 [ASCII Text (16 chars)]...
Page 771 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Label for output relay 17 From 32 to 163 in steps of 1 Relay 18 Output R18 [ASCII Text (16 chars)] Label for output relay 18 From 32 to 163 in steps of 1 Relay 19 Output R19...
Page 772 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [Courier Number (time-seconds)] CB Operate Time CB Operate Time [Courier Number (time-seconds)] Relay Trip Time Relay Trip Time [Courier Number (time-seconds)] Fault Location Fault Location [Courier Number (metres)] Fault Location Fault Location [Courier Number (miles)]...
Page 773 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION VB Pre Flt VB Pre Flt [Courier Number (voltage)] VB Angle Pre Flt VB Angle Pre Flt [Courier Number (degrees)] VC Pre Flt VC Pre Flt [Courier Number (voltage)] VC Angle Pre Flt VC Angle Pre Flt...
Page 774 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION VC Fault VC Fault [Courier Number (voltage)] VC Angle Fault VC Angle Fault [Courier Number (degrees)] VN Fault VN Fault [Courier Number (voltage)] VN Angle Fault VN Angle Fault [Courier Number (degrees)] IA Local...
Page 775 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [Courier Number (time-seconds)] Ch 2 Prop Delay Ch 2 Prop Delay [Courier Number (time-seconds)] 1 bit per elementLSB Started Elements Started Elements String..MSB String [Binary Flag (32)Indexed String] 1 bit per elementLSB Started Elements 2 Started Elements 2...
Page 776 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Fault IB Diff Fault IB Diff [Courier Number (current)] Fault IC Diff Fault IC Diff [Courier Number (current)] Fault IA Bias Fault IA Bias [Courier Number (current)] Fault IB Bias Fault IB Bias [Courier Number (current)]...
Page 777 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Channel Offsets Channel Offsets [Courier Number (decimal)] Channel Scaling Channel Scaling [Courier Number (decimal)] Channel SkewVal Channel SkewVal [Integer] Channel MinVal Channel MinVal [Integer] Channel MaxVal Channel MaxVal [Integer] Format...
Page 778 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [Integer] Dist. Channel 10 Dist. Channel 10 [Integer] Dist. Channel 11 Dist. Channel 11 [Integer] Dist. Channel 12 Dist. Channel 12 [Integer] Dist. Channel 13 Dist. Channel 13 [Integer] Dist.
Page 779 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION This column contains settings for User Curve Data Curve 1 Name Curve 1 Name Default Curve 1 [ASCII Text (32 chars)] Name entered when curve downloaded Time &...
Page 780 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Record Cntl Ref Record Cntl Ref B300 [Menu Cell(2)] Record Ext Ref Record Ext Ref B400 [Menu Cell(2)] Setting Transfer Reset Demand Reset Demand [None (Reset Menu Cell)] Block Xfer Ref Block Xfer Ref B200...
Page 781 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Start IN1>1 Start IN1>2 Start IN1>3 Start IN1>4 Start ISEF>1 Start ISEF>2 Start ISEF>3 Start ISEF>4 Thermal Alarm Start NVD 1 Start NVD 2 Start I2>1 Start I2>2 Start I2>3 Start I2>4...
Page 782 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Start V>2 Start V>A Start V>B Start V>C Start df/dt>1 Start df/dt>2 Start df/dt>3 Start df/dt>4 Delta I2 Low Delta I2 High Delta I1 Low Delta I1 High I2 Low I2 High I1 Low...
Page 783 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Trip I>2 Trip I>3 Trip I>4 Trip Broken Line Trip IN1>1 Trip IN1>2 Trip IN1>3 Trip IN1>4 Trip ISEF>1 Trip ISEF>2 Trip ISEF>3 Trip ISEF>4 Trip Thermal Trip NVD 1 Trip NVD 2 Trip I2>1...
Page 784 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [Courier Number (time-seconds)] Displays time from protection trip to undercurrent elements indicating the CB is open Relay Trip Time Relay Trip Time [Courier Number (time-seconds)] Displays time from protection start to protection trip Fault Location Fault Location [Courier Number (metres)]...
Page 785 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Measured parameter IM Angle Pre Flt IM Angle Pre Flt [Courier Number (degrees)] Measured parameter VA Pre Flt VA Pre Flt [Courier Number (voltage)] Measured parameter VA Angle Pre Flt VA Angle Pre Flt [Courier Number (degrees)]...
Page 786 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [Courier Number (voltage)] Measured parameter VA Angle Fault VA Angle Fault [Courier Number (degrees)] Measured parameter VB Fault VB Fault [Courier Number (voltage)] Measured parameter VB Angle Fault VB Angle Fault [Courier Number (degrees)] Measured parameter...
Page 787 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION IA Bias IA Bias [Courier Number (current)] Measured parameter IB Bias IB Bias [Courier Number (current)] Measured parameter IC Bias IC Bias [Courier Number (current)] Measured parameter Ch 1 Prop Delay Ch 1 Prop Delay [Courier Number (time-seconds)]...
Page 788 Appendix B - Settings and Signals P54A/B/C/E MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION Measured parameter Fault IB rem 2 Fault IB rem 2 [Courier Number (current)] Measured parameter Fault IC rem 2 Fault IC rem 2 [Courier Number (current)] Measured parameter Fault IA rem 3 Fault IA rem 3...
Page 789 P54A/B/C/E Appendix B - Settings and Signals MENU TEXT DEFAULT SETTING AVAILABLE OPTIONS DESCRIPTION [Courier Number (current)] Measured parameter Fault IN rem 3 Fault IN rem 3 [Courier Number (current)] Measured parameter Fault IN rem 4 Fault IN rem 4 [Courier Number (current)] Measured parameter Fault IN rem 5...
Page 790 Appendix B - Settings and Signals P54A/B/C/E B224 P54xMED-TM-EN-1...
Page 791 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION Relay 1 DDB_OUTPUT_RELAY_1 Assignment of signal to drive output Relay 1 Relay 2 DDB_OUTPUT_RELAY_2 Assignment of signal to drive output Relay 2 Relay 3 DDB_OUTPUT_RELAY_3 Assignment of signal to drive output Relay 3 Relay 4 DDB_OUTPUT_RELAY_4 Assignment of signal to drive output Relay 4...
Page 792 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION Relay 30 DDB_OUTPUT_RELAY_30 Assignment of signal to drive output Relay 30 Relay 31 DDB_OUTPUT_RELAY_31 Assignment of signal to drive output Relay 31 Relay 32 DDB_OUTPUT_RELAY_32 Assignment of signal to drive output Relay 32 Opto 1 DDB_OPTO_ISOLATOR_1 From opto input 1 - when opto energized...
Page 793 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION Opto 27 DDB_OPTO_ISOLATOR_27 From opto input 27 - when opto energized Opto 28 DDB_OPTO_ISOLATOR_28 From opto input 28 - when opto energized Opto 29 DDB_OPTO_ISOLATOR_29 From opto input 29 - when opto energized Opto 30 DDB_OPTO_ISOLATOR_30 From opto input 30 - when opto energized...
Page 794 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION IM64 R1 Input 8 DDB_IM64_R1_8_IN IM64 R1 input 8 - is driven by a message from the remote line end IM64 R2 Input 1 DDB_IM64_R2_1_IN IM64 R2 input 1 - is driven by a message from the remote line end IM64 R2 Input 2 DDB_IM64_R2_2_IN IM64 R2 input 2 - is driven by a message from the remote line end...
Page 795 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION IM64 R5 Input 5 DDB_IM64_R5_5_IN IM64 R5 input 5 - is driven by a message from the remote line end IM64 R5 Input 6 DDB_IM64_R5_6_IN IM64 R5 input 6 - is driven by a message from the remote line end IM64 R5 Input 7 DDB_IM64_R5_7_IN IM64 R5 input 7 - is driven by a message from the remote line end...
Page 796 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION Relay Cond 18 DDB_OUTPUT_CON_18 Input to relay 18 output conditioner Relay Cond 19 DDB_OUTPUT_CON_19 Input to relay 19 output conditioner Relay Cond 20 DDB_OUTPUT_CON_20 Input to relay 20 output conditioner Relay Cond 21 DDB_OUTPUT_CON_21 Input to relay 21 output conditioner...
Page 797 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION Timer in 15 DDB_TIMERIN_15 Input to auxiliary timer 15 Timer in 16 DDB_TIMERIN_16 Input to auxiliary timer 16 Timer out 1 DDB_TIMEROUT_1 Output from auxiliary timer 1 Timer out 2 DDB_TIMEROUT_2 Output from auxiliary timer 2...
Page 798 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION Control Input 12 DDB_CONTROL_12 Control input 12 - for SCADA and menu commands into PSL Control Input 13 DDB_CONTROL_13 Control input 13 - for SCADA and menu commands into PSL Control Input 14 DDB_CONTROL_14 Control input 14 - for SCADA and menu commands into PSL...
Page 799 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION Virtual Input 9 DDB_GOOSEIN_9 Virtual Input 9 - received from GOOSE message Virtual Input 10 DDB_GOOSEIN_10 Virtual Input 10 - received from GOOSE message Virtual Input 11 DDB_GOOSEIN_11 Virtual Input 11 - received from GOOSE message Virtual Input 12...
Page 800 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION Virtual Output 6 DDB_GOOSEOUT_6 Virtual output 6 - allows user to control a binary signal which can be mapped via SCADA protocol output to other devices Virtual Output 7 DDB_GOOSEOUT_7 Virtual output 7 - allows user to control a binary signal which can be mapped via SCADA protocol output to other devices Virtual Output 8...
Page 801 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION Test Loopback DDB_LOOPBACK_TEST Loopback test in service (external or internal) Test IM64 DDB_IM64_TEST_MODE Indication that relay is in test mode VTS Indication DDB_VTS_INDICATION VTS Indication CT Fail Alarm DDB_CTS_INDICATION CTS indication alarm (CT supervision alarm) Remote CT Alarm...
Page 802 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION possible for them to fail to resolve this in which case they produce the DDB_CONFIGURATION_ERROR alarm Re-Config Error DDB_RE_CONFIGURATION_ERROR Indicates that RESTORE or RECONFIGURE or CONFIGURE operations have failed Max Prop.
Page 803 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION EIA(RS)232 InterMiCOM Channel Failure alarm. No messages were received during the alarm time setting Backup Setting DDB_BACKUP_DATA_IN_USE This is an alarm that is ON if any setting fail during the setting changing process. If this happens, the relay will use the last known good setting Reserved DDB_DNPEV_BAD_SETTINGS_ALARM...
Page 804 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION V<1 Timer Block DDB_PUV_1_TIMER_BLOCK Block phase undervoltage stage 1 time delayed trip V<2 Timer Block DDB_PUV_2_TIMER_BLOCK Block phase undervoltage stage 2 time delayed trip V>1 Timer Block DDB_POV_1_TIMER_BLOCK Block phase overvoltage stage 1 time delayed trip V>2 Timer Block...
Page 805 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION Recon Interlock DDB_RECONFIGURATION_INTERLOCK This must be energized (along with DDB 455 - inhibit C Diff) at the time that a relay configuration is changed from 3 ended to 2 ended scheme.
Page 806 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION To enable SOTF logic by an external pulse. When this input is energized by en external pulse, SOTF becomes enabled during “SOTF Pulse” time setting RP1 Read Only DDB_REMOTEREADONLY_RP1 Enables RP1 Read Only RP2 Read Only...
Page 807 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION SG1 is active if both DDB 542 & DDB 543=0 SG4 is active if both DDB 542 & DDB 543=1 Clear Statistics DDB_CLEAR_STATISTICS To reset all statistics values cumulated on the relay. If mapped, the input for this signal could come from a command of the remote end (DDB 1020 - clear stats cmd -) via IM64 I2>...
Page 808 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION Perm InterTrip DDB_PERMISSIVE_INTERTRIP Permissive intertrip Stub Bus Trip DDB_STUB_BUS_TRIP Stub bus trip df/dt> Inhibit DDB_DFDT_INHIBIT Inhibit df/dt protection df/dt>1 Tmr Blk DDB_DFDT_1_TIMER_BLOCK Block df/dt Stage 1 Timer df/dt>2 Tmr Blk DDB_DFDT_2_TIMER_BLOCK Block df/dt Stage 2 Timer...
Page 809 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION I>4 Trip B DDB_POC_4_PH_B_TRIP 4th stage phase overcurrent trip phase B I>4 Trip C DDB_POC_4_PH_C_TRIP 4th stage phase overcurrent trip phase C IN>1 Trip DDB_EF1_1_TRIP 1st stage stand by earth fault (SBEF) protection trip IN>2 Trip DDB_EF1_2_TRIP 2nd stage stand by earth fault (SBEF) protection trip...
Page 810 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION Pole Discrepancy DDB_POLE_DISCREPENCE_TRIP Pole Discrepancy (signal raised when a pole discrepancy state is detected on CB) VN>1 Trip DDB_RESOV_1_TRIP Residual overvoltage stage 1 trip VN>2 Trip DDB_RESOV_2_TRIP Residual overvoltage stage 2 trip Fault REC TRIG DDB_FAULT_RECORDER_START...
Page 811 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION ISEF>1 Start DDB_SEF_1_START 1st stage sensitive earth fault (SEF) overcurrent start ISEF>2 Start DDB_SEF_2_START 2nd stage sensitive earth fault (SEF) overcurrent start ISEF>3 Start DDB_SEF_3_START 3rd stage sensitive earth fault (SEF) overcurrent start ISEF>4 Start DDB_SEF_4_START 4th stage sensitive earth fault (SEF) overcurrent start...
Page 812 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION VT supervision slow block - blocks elements which would otherwise maloperate some time after a fuse failure event occurs Bfail1 Trip 3ph DDB_CBF1_TRIP_3PH Three phase output from circuit breaker failure logic, stage 1 Bfail2 Trip 3ph DDB_CBF2_TRIP_3PH Three phase output from circuit breaker failure logic, stage 2...
Page 813 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION TOR Active DDB_TOR_ACTIVE Trip on re-close protection is active - indicated TOC delay timer has elapsed after circuit breaker opening, and remains in-service on auto- reclosure for the duration of the trip on close window SOTF Active DDB_SOTF_ACTIVE Switch on to fault protection is active - in service on manual breaker closure, and then remains in-service for the duration of the trip on close...
Page 814 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION Inhibit Cmp V1>1 DDB_INHIBIT_COMP_OV1 Inhibit the first stage compensated overvoltage element Inhibit Cmp V1>2 DDB_INHIBIT_COMP_OV2 Inhibit the second stage compensated overvoltage element Cmp V1>1 Tim Blk DDB_PCOV_1_TIMER_BLOCK Block the first stage compensated overvoltage element Cmp V1>2 Tim Blk DDB_PCOV_2_TIMER_BLOCK...
Page 815 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION Started Phase N DDB_FLTREC_STRT_N Started phase N (fault involves ground) - must be assigned, as this sets the start flag used in records, and on the LCD display 1024 LED1 Red DDB_OUTPUT_TRI_LED_1_RED...
Page 816 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION 1052 FnKey LED7 Red DDB_OUTPUT_TRI_LED_15_RED Programmable function key LED 7 red is energized 1053 FnKey LED7 Grn DDB_OUTPUT_TRI_LED_15_GRN Programmable function key LED 7 green is energized 1054 FnKey LED8 Red DDB_OUTPUT_TRI_LED_16_RED Programmable function key LED 8 red is energized...
Page 817 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION 1080 FnKey LED3 ConR DDB_TRI_LED_RED_CON_11 Assignment of signal to drive output function key LED 3 red. This LED is associated with function key 3 1081 FnKey LED3 ConG DDB_TRI_LED_GRN_CON_11 Assignment of signal to drive output function key LED 3 green.
Page 818 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION 1105 Function Key 10 DDB_FN_KEY_10 Function key 10 is activated. In ‘Normal’ mode it is high on keypress and in ‘Toggle’ mode remains high/low on single keypress 1024 LED 1 DDB_OUTPUT_LED_1...
Page 819 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION 1131 SignalFail Ch2Tx DDB_SIGNALLING_FAIL_CH2_TX Transmission of messages on channel 1 has stopped 1133 Ch2 Mux Clk DDB_MUX_CLK_ERROR_CH2 This is an alarm that appears if the channel 2 baud rate is outside the limits 52kbits/s or 70 kbits/s 1134 Ch2 Signal Lost DDB_IEEE37_94_CH2_LOSS_OF_SIG...
Page 820 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION 1165 F>1 Trip DDB_OFREQ_1_TRIP Over frequency Stage 1 Trip 1166 F>2 Trip DDB_OFREQ_2_TRIP Over frequency Stage 2 Trip 1167 Inhibit F<1 DDB_INHIBIT_UF1 Inhibit Stage 1 Underfrequency protection 1168 Inhibit F<2 DDB_INHIBIT_UF2...
Page 821 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION 1198 PSL Int 5 DDB_PSLINT_5 PSL Internal Node 1199 PSL Int 6 DDB_PSLINT_6 PSL Internal Node 1200 PSL Int 7 DDB_PSLINT_7 PSL Internal Node 1201 PSL Int 8 DDB_PSLINT_8 PSL Internal Node 1202...
Page 822 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION 1227 PSL Int 34 DDB_PSLINT_34 PSL Internal Node 1228 PSL Int 35 DDB_PSLINT_35 PSL Internal Node 1229 PSL Int 36 DDB_PSLINT_36 PSL Internal Node 1230 PSL Int 37 DDB_PSLINT_37 PSL Internal Node 1231...
Page 823 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION 1256 PSL Int 63 DDB_PSLINT_63 PSL Internal Node 1257 PSL Int 64 DDB_PSLINT_64 PSL Internal Node 1258 PSL Int 65 DDB_PSLINT_65 PSL Internal Node 1259 PSL Int 66 DDB_PSLINT_66 PSL Internal Node 1260...
Page 824 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION 1285 PSL Int 92 DDB_PSLINT_92 PSL Internal Node 1286 PSL Int 93 DDB_PSLINT_93 PSL Internal Node 1287 PSL Int 94 DDB_PSLINT_94 PSL Internal Node 1288 PSL Int 95 DDB_PSLINT_95 PSL Internal Node 1289...
Page 825 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION 1381 Group Alarm DDB_GROUP_ALARM This is an output signal available in the PSL, which can be mapped in IEC870-5-103 to a major problem normally linked to the watchdog 1382 AR On Pulse DDB_AR_ON_PULSE...
Page 826 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION DDB mapped in PSL from opto input (Bus VT secondary MCB tripped or VT fail detected by external VTS scheme), or signal from host relay VTS scheme 1522 Inhibit LL DDB_INHIBIT_LIVE_LINE...
Page 827 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION Output DDB can be applied to inhibit reclose by adjacent scheme until local autoreclose scheme confirms it is OK to close CB 1567 1P Reclaim Time DDB_SP_RECLAIM_TIME Single Phase AR reclaim time running 1568 1P Reclaim TComp...
Page 828 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION 1617 PSL Int 102 DDB_PSLINT_102 PSL Internal Node 1618 PSL Int 103 DDB_PSLINT_103 PSL Internal Node 1619 PSL Int 104 DDB_PSLINT_104 PSL Internal Node 1620 PSL Int 105 DDB_PSLINT_105 PSL Internal Node 1621...
Page 829 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION 1646 PSL Int 131 DDB_PSLINT_131 PSL Internal Node 1647 PSL Int 132 DDB_PSLINT_132 PSL Internal Node 1648 PSL Int 133 DDB_PSLINT_133 PSL Internal Node 1649 PSL Int 134 DDB_PSLINT_134 PSL Internal Node 1650...
Page 830 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION 1699 IEC Usr 02 Close DDB_IEC_USR_CLS_2 IEC61850 User Dual Point Status 2 Closed 1700 IEC Usr 03 Open DDB_IEC_USR_OPN_3 IEC61850 User Dual Point Status 3 Open 1701 IEC Usr 03 Close DDB_IEC_USR_CLS_3 IEC61850 User Dual Point Status 3 Closed...
Page 831 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION 1735 Quality VIP 8 DDB_VIP_QUALITY_8 GOOSE virtual input 8 - provides the Quality attributes of any data object in an incoming GOOSE message 1736 Quality VIP 9 DDB_VIP_QUALITY_9 GOOSE virtual input 9 - provides the Quality attributes of any data object in an incoming GOOSE message 1737...
Page 832 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION 1764 PubPres VIP 5 DDB_VIP_PUB_PRES_5 GOOSE virtual input 5- indicates if the GOOSE publisher responsible for publishing the data that derives a virtual input is present. 1765 PubPres VIP 6 DDB_VIP_PUB_PRES_6 GOOSE virtual input 6- indicates if the GOOSE publisher responsible for publishing the data that derives a virtual input is present.
Page 833 P54A/B/C/E Appendix B - Settings and Signals ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION 1795 No signal Rec. DDB_NO_SIGNAL_RECEIVED Indicate the communication channel don't receive signal 1796 CT1 R3 i1> DDB_CTS_R3_1_I1 CTS R3 1 I1 1797 CT1 R3 i2/i1> DDB_CTS_R3_1_I2I1_L CTS R3 1 I2I1 L 1798 CT1 R3 i2/i1>>...
Page 834 Appendix B - Settings and Signals P54A/B/C/E ORDINAL SIGNAL NAME ELEMENT NAME DESCRIPTION 2028 Timer in 29 DDB_TIMERIN_29 Input to Auxiliary Timer 29 2029 Timer in 30 DDB_TIMERIN_30 Input to Auxiliary Timer 30 2030 Timer in 31 DDB_TIMERIN_31 Input to Auxiliary Timer 31 2031 Timer in 32 DDB_TIMERIN_32...
Page 835 APPENDIX C WIRING DIAGRAMS...
Page 836 Appendix C - Wiring Diagrams P54A/B/C/E P54xMED-TM-EN-1...
Page 837 P54A/B/C/E Appendix C – Wiring Diagrams CORTEC DRAWING- MODEL EXTERNAL CONNECTION DIAGRAM TITLE ISSUE OPTION* SHEET Px4x COMMS OPTIONS MICOM Px40 PLATFORM 10Px4001-1 A to R CURRENT DIFF 1 RELAY 8 INPUTS, 8 OUTPUTS & SEF (40TE) 10P54A01-1 P54A A to R CURRENT DIFF 1 RELAY 8 INPUTS, 8 OUTPUTS &...
Page 838 Issue: Revision: Title: EXTERNAL CONNECTION DIAGRAM: COMMS OPTIONS DRAWING OUTLINE UPDATED. CID BLIN-8BHLDT MICOM Px40 PLATFORM Date: 30/11/2010 Name: W.LINTERN ALSTOM GRID UK LTD Sht: CAD DATA 1:1 DIMENSIONS: mm 10Px4001 Substation Automation Solutions DO NOT SCALE Next Date: Chkd: (STAFFORD) Sht:...
Page 839 DIRECTION OF FORWARD CURRENT FLOW PHASE ROTATION MiCOM P54A (PART) MiCOM P54A (PART) OPTO 1 WATCHDOG CONTACT NOTE 3. WATCHDOG OPTO 2 CONTACT OPTO 3 RELAY 1 OPTO 4 RELAY 2 EIA485/ SEE DRAWING OPTO 5 KBUS RELAY 3 10Px4001 PORT RELAY 4 OPTO 6...
Page 840 Issue: Revision: Title: EXTERNAL CONNECTION DIAGRAM: CURRENT DIFF 1 RELAY SWOO-AB5E6D. INITIAL ISSUE. 8 INPUTS, 8 OUTPUTS & SEF (40TE) Date: 07/10/2016 Name: S.WOOTTON ALSTOM GRID UK LTD Sht: CAD DATA 1:1 DIMENSIONS: mm 10P54A01 Substation Automation Solutions DO NOT SCALE Next Date: Chkd:...
Page 841 DIRECTION OF FORWARD CURRENT FLOW PHASE ROTATION MiCOM P54B (PART) MiCOM P54B (PART) OPTO 1 WATCHDOG CONTACT NOTE 4. WATCHDOG OPTO 2 CONTACT OPTO 3 RELAY 1 OPTO 4 RELAY 2 EIA485/ SEE DRAWING OPTO 5 KBUS RELAY 3 10Px4001 PORT RELAY 4 OPTO 6...
Page 842 Issue: Revision: Title: EXTERNAL CONNECTION DIAGRAM: CURRENT DIFF 2 RELAY SWOO-AB5E6D. INITIAL ISSUE. 8 INPUTS, 8 OUTPUTS & SEF (40TE) Date: 07/10/2016 Name: S.WOOTTON ALSTOM GRID UK LTD Sht: CAD DATA 1:1 DIMENSIONS: mm 10P54B01 Substation Automation Solutions DO NOT SCALE Next Date: Chkd:...
Page 843 DIRECTION OF FORWARD CURRENT FLOW PHASE ROTATION MiCOM P54C (PART) MiCOM P54C (PART) WATCHDOG CONTACT OPTO 1 WATCHDOG CONTACT NOTE 5. OPTO 2 RELAY 1 EIA485/ SEE DRAWING KBUS 10Px4001 PORT OPTO 3 RELAY 2 RELAY 3 OPTO 4 RELAY 4 OPTO 5 AC OR DC RELAY 5...
Page 844 Issue: Revision: Title: EXTERNAL CONNECTION DIAGRAM: CURRENT DIFF 2 RELAY SWOO-AB5E6D. INITIAL ISSUE. 16 INPUTS, 8 OUTPUTS & SEF (60TE) Date: 07/10/2016 Name: S.WOOTTON ALSTOM GRID UK LTD Sht: CAD DATA 1:1 DIMENSIONS: mm 10P54C01 Substation Automation Solutions DO NOT SCALE Next Date: Chkd:...
Page 845 DIRECTION OF FORWARD CURRENT FLOW PHASE ROTATION MiCOM P54C (PART) MiCOM P54C (PART) WATCHDOG CONTACT OPTO 1 WATCHDOG CONTACT NOTE 5. OPTO 2 RELAY 1 EIA485/ SEE DRAWING KBUS 10Px4001 PORT OPTO 3 RELAY 2 RELAY 3 OPTO 4 RELAY 4 OPTO 5 AC OR DC RELAY 5...
Page 846 DEFAULT SETTING Inhibit Diff CONTACT Recon Interlock CONTACT DEFAULT SETTING RELAY 1 Trip Diff / Z1(1) SEE NOTE 1 Aid 1 Receive SignalingFail RELAY 2 SEE NOTE 1 Aid 1 COS/LGS RELAY 3 Any Trip Reset LEDs RELAY 4 General Alarm External Trip A RELAY 5 IM64 1...
Page 847 DIRECTION OF FORWARD CURRENT FLOW (SEE NOTE 8) MiCOM P54E (PART) WATCHDOG CONTACT PHASE ROTATION WATCHDOG SEE NOTE 6 CONTACT MiCOM P54E (PART) RELAY 1 RELAY 2 OPTO 1 RELAY 3 NOTE 5. OPTO 2 RELAY 4 OPTO 3 RELAY 5 OPTO 4 RELAY 6 OPTO 5...
Page 848 DEFAULT SETTING WATCHDOG CONTACT WATCHDOG DEFAULT SETTING CONTACT SEE NOTE 1 SEE NOTE 1 RELAY 1 RELAY 2 SEE NOTE 1 RELAY 3 RELAY 4 RELAY 5 RELAY 6 RELAY 7 (PART) RELAY 8 RELAY 9 RELAY 10 RELAY 11 RELAY 12 RELAY 13 RELAY 14...
Page 850 Imagination at work Grid Solutions St Leonards Building Redhill Business Park Stafford, ST16 1WT, UK +44 (0) 1785 250 070 www.gegridsolutions.com/contact © 2017 General Electric. All rights reserved. Information contained in this document is indicative only. No representation or warranty is given or should be relied on that it is complete or correct or will apply to any particular project.

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GE P4A Technical Manual

Chapter 1 Introduction

Chapter Overview

Foreword

Product Scope

Features and Functions

Logic Diagrams

Functional Overview

Chapter 2 Safety Information

Chapter Overview

Health and Safety

Symbols

Installation, Commissioning and Servicing

Decommissioning and Disposal

Regulatory Compliance

Chapter 3 Hardware Design

Chapter Overview

Hardware Architecture

Mechanical Implementation

Front Panel

Rear Panel

Boards and Modules

Chapter 4 Software Design

Chapter Overview

Sofware Design Overview

System Level Software

Platform Software

Protection and Control Functions

Chapter 5 Configuration

Chapter Overview

Settings Application Software

Using the HMI Panel

Line Parameters

Date and Time Configuration

Settings Group Selection

Chapter 6 Current Differential Protection

Chapter Overview

Current Differential Protection Principle

Charging Current Compensation

Synchronisation of Current Signals

CT Saturation

CT Compensation

Current Differential Intertripping

Stub Bus Differential Protection

Application Notes

Chapter 7 Autoreclose

Chapter Overview

Introduction to Autoreclose

Autoreclose Implementation

Autoreclose System Map

Logic Modules

Quick Links

Troubleshooting

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Summary of Contents for GE P4A