Direct Inputs And Outputs - GE B90 Instruction Manual

Low impedance bus differential system
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PRODUCT SETUP

5.3.17 Direct inputs and outputs

5.3.17.1 Menu
SETTINGS  PRODUCT SETUP  DIRECT I/O
 DIRECT I/O
5
This option is available when an Inter-Relay Communications card is specified at the time of ordering (see the
Order Code tables). With the option, direct inputs/outputs display by default. When you enable the
teleprotection feature, direct I/O is not visible.
Direct inputs and outputs exchange status information (inputs and outputs) between UR-series relays connected directly
via type 7 digital communications cards. The mechanism is very similar to IEC 61850 GOOSE, except that communications
takes place over a non-switchable isolated network and is optimized for speed. On type 7 cards that support two channels,
direct output messages are sent from both channels simultaneously. This effectively sends direct output messages both
ways around a ring configuration. On type 7 cards that support one channel, direct output messages are sent only in one
direction. Messages are resent (forwarded) when it is determined that the message did not originate at the receiver.
Teleprotection inputs/outputs and direct inputs/outputs are mutually exclusive. As such, they cannot be used
simultaneously. Once teleprotection inputs and outputs are enabled, direct inputs and outputs are blocked, and
vice versa.
B90 supports 96 Direct I/Os at 64 or 128 kbps rate and 256 Direct I/Os at 213 kbps rate. With 64 or 128 kbps rate, the B90
can exchange Direct I/Os with other URs, while at 213 kbps B90s can exchange between each other's only. Functionality at
213 kbps is possible only with firmware 7.4 or higher and with CPU FPGA revision 2.02 or higher. The CPU FPGA version can
be confirmed in the
be upgraded in the field; see the upgrade procedures on the B90 Support Documents page of the GE Multilin web site. In
version 7.42 and later, when connected by serial cable, use Maintenance > Update FPGA Firmware.
Direct output message timing is similar to GOOSE message timing. Integrity messages (with no state changes) are sent at
least every 1000 ms. Messages with state changes are sent within the main pass scanning the inputs and asserting the
outputs unless the communication channel bandwidth has been exceeded. Two self-tests are performed and signaled by
the following FlexLogic operands:
DIRECT RING BREAK
from a UR-series relay are not being received back by the relay.
5-122
DIRECT OUTPUTS
DEVICE ID: 1
DIRECT I/O CH1 RING
CONFIGURATION: Yes
DIRECT I/O CH2 RING
CONFIGURATION: Yes
DIRECT I/O DATA
RATE: 64 kbps
DIRECT I/O CHANNEL
CROSSOVER: Disabled
 CRC ALARM CH1
 CRC ALARM CH2
 UNRETURNED
 MESSAGES ALARM CH1
 UNRETURNED
 MESSAGES ALARM CH2
ACTUAL VALUES > PRODUCT INFO > FIRMWARE REVISIONS > FPGA PROGRAM REVISION
(direct input/output ring break). This FlexLogic operand indicates that direct output messages sent
Range: 1 to 16 in steps of 1
Range: Yes, No
Range: Yes, No
Range: 64 kbps, 128 kbps, 213 kbps
Range: Disabled, Enabled
See page 5-127
See page 5-128
B90 LOW IMPEDANCE BUS DIFFERENTIAL SYSTEM – INSTRUCTION MANUAL
CHAPTER 5: SETTINGS
menu. CPU FPGA can

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