Aiwa CDC-Z127 Service Manual page 31

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Pin No. Pin Name
37 HFL
38 SLOF
39 CV-
40 CV+
41 RFSM
42 RFS-
43 SLC
44 SLI
45 D-GND
46 FSC
47 TBC
48 NC
49 DEF
50 CLK
51 CL
52 DAT
53 CE
54 DRF
TE
L 13942296513
55 FSS
56 VCC2
57 REFI
58 VR
59 LF2
60 PH1
61 BH1
62 LDD
63 LDS
64 VCC1
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I/O
The HFL (high frequency level) signal is used to judge whether the main beam is positioned on
O
the pit or on the mirror.
I Sled servo off control input.
I CLV error signal input from the DSP.
O RF output.
O Set the RF gain and the EFM singal's 3T compensation constant together with the RFSM pin.
The SLC (slice level control) signal is output to control the DSP's data slice level of the RF
O
waveform.
I Input to control the DSP's data slice level.
- Ground of digital signals.
O Output for the focus search smoothing capacitor.
I The TBC (tracking balance control) signal sets the EF balance variation range.
- Not connected.
O Disc defect detection output.
I Reference clock input. 4.23 MHz is input from the DSP.
I Microprocessor command clock input.
I Microprocessor command data input.
I Microprocessor chip enable input.
O DRF (detect RF) is an output to detect the RF level.
The FSS (focus search select) signal switches the focus search modes (+/-search / +search with
I
respect to the reference voltage). (Connected to D-GND)
- VCC of servo and digital circuits.
- For the connection of bypass capacitor for the reference voltage.
O Reference voltage output.
- Set the time constant for disc defect detection.
- For the connection of a capacitor to hold the RF signal peak.
- For the connection of a capacitor to hold the RF signal bottom.
O APC circuit output.
I APC circuit input.
- VCC of RF signal circuits.
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