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HP Edgeline EL1000 User Manual: Hpe Emc Compliance Testing; System Synchronization Clock Specifications

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HPE EMC compliance testing

Emissions classification
EMC
NOTE:
Product conformance to cited product specifications is based on sample (type) testing, evaluation,
or assessment. This product or family of products is eligible to bear the appropriate compliance
logos and statements.

System synchronization clock specifications

10 MHz system reference clock: PXI_CLK10
Specification
Maximum slot-to-slot skew
Accuracy
Maximum jitter
Duty factor
Unloaded signal swing
NOTE:
For other specifications, see 'PXI-1 Hardware Specification' at the PXI Systems Alliance website
(http://www.pxisa.org/userfiles/files/Specifications/PXIHWSPEC22.pdf).
100 MHz system reference clock: PXIe_CLK100 and PXIe_SYNC100
Specification
Maximum slot-to-slot skew
Accuracy
FCC rating
Normative standards
Value
1 ns
±25 ppm max (guaranteed over the operating
temperature range)
5 ps RMS phase jitter (10 Hz to 1 MHz range)
45% to 55%
3.3 V ±0.3 V
Value
200 ps
±25 ppm max (guaranteed over the operating
temperature range)
Class A
CISPR 22
EN55022
EN55024
FCC CFR 47
Pt 15
ICES-003
CNS13438
K22
K24
EN 61000-3-2
EN 61000-3-3
EN 60950-1
IEC 60950-1
Table Continued
HPE EMC compliance testing
55

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