Cisco ONS 15454 DWDM Reference Manual page 133

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Chapter 2
Common Control Cards
Figure 2-2
TCC2P
FAIL
PWR
A
ACT/STBY
CRIT
MAJ
MIN
REM
SYNC
ACO
ACO
LAMP
RS-232
TCP/IP
78-18343-02
TCC2P Faceplate and Block Diagram
-48V PWR
Monitors
Real Time
Clock
B
Serial
Debug
400MHz
Processor
SDRAM Memory
& Compact Flash
Faceplate
Ethernet Port
Faceplate
EIA/TIA 232 Port
System
Timing
FPGA
DCC
Processor
MCC1
MCC2
SMC1
SCC2
SCC3
FCC1
Communications
Processor
SCC1
SCC4
FCC2
Ethernet Switch
EIA/TIA 232
Craft Interface
Note: Only 1 EIA/TIA 232 Port Can Be Active -
Backplane Port Will Supercede Faceplate Port
Cisco ONS 15454 DWDM Reference Manual, R8.5
2.3 TCC2P Card
BACKPLANE
Ref Clocks
(all I/O Slots)
BITS Input/
TCCA ASIC
SCL Links to
SCL Processor
All Cards
HDLC
Message
Bus
Modem
Interface
Interface
(Not Used)
Mate TCC2
HDLC Link
Ethernet
Phy
Backplane
Ethernet Port
(Shared with
Mate TCC2)
Mate TCC2
Ethernet Port
Backplane
EIA/TIA 232 Port
(Shared with
Mate TCC2)
Output
Modem
2-7

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