Motorola APX 3000 Basic Service Manual page 40

3-8 Basic Theory of Operation: Controller Section
The ARM controller core of the OMAP processor handles the power up sequence of all devices,
including firmware upgrades, and all operating system tasks that are associated with FLASH and
SDRAM memories and user interface communication. The FLASH memory (64 MB) is required to
store the firmware, tuning, and Codeplug settings, which upon initialization get read and stored into
SDRAM (32MB) for execution. The ARM and DSP core jointly control and configure audio, wireless
and RF devices linked to the Serial Peripheral Interface (SPI) and Synchronous Serial Interface
(SSI) buses to enable radio FM and optional wireless communication protocols. For encryption, a
separate ARM processor is used (MACE) to encode and decode encryption packets coming in from
the main OMAP processor through the SSI interface. Its firmware is flashed via the main processor
during an upgrade request to its internal FLASH memory.
The power supply and most clocks to the controller devices are provided by the MAKO IC and
external switching and linear regulators on board. A Complex Programmable Logic Array (CPLD) IC
divides the 24.576 MHz clock from MAKO to source OMAP's 32 kHz Real Time Clock, and MACE's
4 MHz main clock. OMAP's main clock is supplied externally from an on board 12 MHz crystal.
The radio only supports microphone and speaker connection for external accessories. The external
accessory speaker is driven by a Class AB audio amplifier on the MAKO IC that is capable of
delivering 0.5 W of power into a 16 Ohm as a minimum load. The external speaker path uses the
CODEC for volume control and to convert the audio signal from digital to analog. The external
microphone uses the CODEC's ADC to deliver digital audio samples to the DSP controller.
The user interface block consists of a Bluetooth LED, top controls, side control and the accessory
side connector. The side connector (Universal Connector) provides audio, USB, RS232
communication for accessories. All signals to and from the connector go through flexes before
reaching the microcontroller and other devices on the main board.
The radio also has integrated feature of Global Positioning System (GPS) and Bluetooth with Man-
down feature (depending on radio model) (see Figure 3-11). The GPS and Bluetooth Combo RF
chipset (NL5500) is located on the Main board together with the GPS/RF Diplexer circuitry and
Bluetooth Front-End circuitry. The GPS receiver section of the GPS/BT combination IC interfaces
with the OMAP processor through a dedicated UART port. The GPS receiver also has a dedicated
reset controlled solely by the OMAP processor. The GPS/Bluetooth IC (NL5500) taps the GPS signal
from transceiver path and processes the location information before relaying to the OMAP processor
via UART lines. The clock supplies to NL5500 included a 26MHz TCXO and 32kHz clock from
CPLD.