Korg DW-8000 Service Manual page 32

5.
Main
circuit explanation
1
)
Keyboard
scanning
The
CPU
outputs
3-bit
addresses
in
the range
A0~A2
which
are
decoded by
the address decoder
HC138
(IC25, IC28).
The
output
of
this
decoder
goes
through connector
CN10
(first
contact)
and
CN1
1
(second contact) to the
keyboard
matrix
for scanning.
Keyboard
matrix
output goes from connector
CN6
through
the inverting octal
buffer
HC240
(IC16
HD
specification)
to be passed to the data bus
DO-D7.
2)
Key
on/off data and
velocity
data
Velocity data
is
computed
using the
CPU
timer to
measure
the time
from
when
the
key contact
leaves the
first
contact
until
it
reaches the second contact.
KEY ON
data
is
generated
when
the
key
contact reaches
the
second
contact.
Key
off data
is
generated
when
the
first
contact
is
reached
after leaving the
second
contact.
3)
After
Touch
data
The ESK-901 keyboard's
after
touch unit (sandwich of
metal
plate,
conductive
rubber,
and metal
plate)
produces
impedance
variations
which
KLM-759
detects
as
analog
voltages over the range of
0V~3.5V.
The
voltage passes
through the multiplexer
4051
(IC5)
to the
CPU
where,
via a
DAC,
it
changes the control voltage
for
the
effect.
4)
DWGS
system
This
board contains the
DWGS
basic
system.
The
purpose
of
this
system
is
to get pitch
and
waveform
data
from
the
CPU
bus and output
a cyclic (repetitive)
waveform
of
con-
stant
amplitude.
Oscillator
operation
The PAI (phase angle
increment) value
and
PAR
(phase
angle register)
value
are
added and
the result
is
stored again
in
the
PAR. The
PAR
value
is
used
as
the
wave
table ad-
dress.
The wave table stores
different
harmonic
configura-
tion data for
each octave
on the
keyboard.
IC47
(MB64H1
29)
performs the processing
needed
to use
the
PAR
value as
the
wave
table address.
Finally,
data read
from
the
wave
table
is
converted to an
analog
waveform by
a
D/A
converter.
Time
division
multiplexing enables dual oscillator
6-voice
sound
source
capability.
Maximum simultaneous output
of this
system
is
8
voices
x 2
oscillators.
Note: Given
a
sampling frequency of
50 kHz,
PAI
data
N = 2
18
x f/50
x
10
3
(where
f
is
the pitch
frequency)
is
rounded to
an
integer
value for
N and converted
to
a
hexadecimal
number.
The main
LSI chips are
the
CMOS
gate array
IC47 (MB-
64H129) and IC60 (MB62H133),
the
wave-table
256K
mask
ROM
IC45 and IC46
(HN613256), the ten
TTL
64-
bit
RAM
chips for
PAI
& PAR
(IC48-IC57; SI 89), the
8-bit
D/A
converter
IC42 (DAC-08), decoder
chips
IC50,
IC59 (LS244),
KLM-662
IC16 (LS175), IC14,
IC15
(LS138),
as
well as
S/H
analog switches
(1017^1020; 4066)
and
OP
AMPS
(IC21~IC25; 072).
IC60
(MB62H1
33)
is
a
64-pin LSI with about
800
gates
handling major aspects of the
system including the
CPU
interface,
timing
generation,
and
adder.
CPU BUS
IC60
(MB62H133)
74LS189
x 10
IC48-IC57
IC66 (62H133)
IC47
(64H129)
64K
ROM
IC45. IC46
DAC-08
HC138 +
4066 +072
-
35
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