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9. REFERENCE: EXTERNAL CONNECTION EXAMPLES
9.2 3rd Boosting + Regulator
Perform 3rd boosting in the negative direction for input voltage VI, and generate the stabilized voltage in the
VREG pin.
Figure 9.2 shows a connection example.
V
REG
V
DD
VI
Figure 9.2 Setting conditions
Internal clock
Booster
Regulator
Power-off method
Set the POFF1X pin to level LOW (VI); all circuits will be turned off.
About regulator
For information about the regulator setting method and notes, see Section 5.4.
Other setting conditions
(1) When using the high output mode
Connect the FC pin to VI.
(2) When changing the temperature coefficient CT
Change the TC1 and TC2 pins as shown in Table 5.3.
20
CO
+
CREG
+
R1
R2
+
CI
Figure 9.2 3rd boosting + regulator connection example
:
ON (Low output mode)
:
ON
:
ON (Select CT0 = -0.05%/°C.)
EPSON
1
1
VO
C2P
16
2
VRI
C2N
15
3
V
X3N
14
REG
4
RV
C1N
13
5
V
C1P
12
DD
6
FC
VI
11
7
TC1
POFF1X
10
8
TC2
POFF2X
9
S1F76540M0C Series Technical Manual
+
C2
C1
+
(Rev.1.1)
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