JVC DR-MH300SAA Service Manual page 14

DIGITAL 5 0
IEEE1394
controller
PHY_RESET[L]
5
IC1801
PHY_LREQ PHY_CLK
PHY_CNA PHY_CTL[0],[1]
PHY_DATA[0-7] PHY_LPS
PHY_LINK_ON
SDRAM_DQ16 to 31
SDRAM_A_17
4
RA1609 to
SDRAM_DQ0 to 15
RA1612
SDRAM_A0 to 16
SDRAM_CKE
SDRAM_RAS_L
SDRAM_CAS_L
SDRAM_WE_L
SDRAM_DQM0 to 3
3
SDRAM_DQS0 to 3
R1653 to R1660
SDRAM_CLK0,1
SDRAM_CLK_L0,1
2
VI_D2 to D9 VIDEO_27M AI_SCLK AI_FSYNC AI_MCLK AI_D[0]
VIDEO_MUTE[H] EPG_V_SEL E5_CVBS_OUT E5_SY_OUT
E5_SC_OUT E5_Y_OUT E5_PB_OUT E5_PR_OUT VIDEO_RST[L]
DAC_RST[L] SPI_CLK K_BUS_CLK K_BUS_REQ SYS_RESET[L]
K_BUS_OUT K_BUS_IN A_MUTE2[H] A_DAC_CS VIDEO_CS
Media
VIDEO_RXD SPI_MOSI
processor
IC1401
ATA_DMAACK[L] ATA_INTRQ ATA_ADD0 to 4 ATA_DIOR[L]
ATA_DIOW[L] ATA_IORDY ATA_DAT0 to 15 ATA_RESET
ATA_DMARQ ATA2_DMAACK[L] ATA2_INTRQ ATA2_ADD0 to 4
ATA2_DIOR[L] ATA2_DIOW[L] ATA2_IORDY ATA2_DAT0 to 15
ATA2_RESET ATA2_DMARQ
1
RD/WR[L] ALE OE[L]/LDS[L] MADD1 to 22 CS0 to 3 SYS_RESET[L]
UWE[L]/UDS[L] EPG_INT[L]
A
J4212
TPA+ TPA- TPB+ TPB- IEEE1394
terminal
IEEE1394 Section (SHEET 11)
DDR_DQ16 to 31
RA1613 to
RA1616
DDR SDRAM DDR SDRAM
DDR_DQ0 to 15
IC1601 IC1603 IC1602 IC1604
DDR_BA0,1
DDR_A0 to 12
RA1625 to
RA1628
DDR_CKE
DDR_RAS_L
DDR_CAS_L
DDR_WE_L
RA1633
DDR_DQM0 to 3
DDR_DQS0 to 3
DDR_CLK0,1
DDR_CLK_L0,1
R1613 to
R1616
DDR-SDRAM Section (SHEET 12)
Media processor section (SHEET 13)
B C
Video interface section (SHEET 14)
D E
2-7 2-8
SYS_RESET[L] P_CTL[H] A_MUTE[H]
P_MUTE[H] Y_OUT C_OUT C/R_OUT Pr/G_OUT
Y/V_OUT Pb/B_OUT C_IN/R_IN YV_IN
Video
decoder
IC1001 16M SDRAM
IC1002
AI_MCLK AI_FSYNC AI_D[0] DAC_SDA DAC_SCL A_DAC_CS DAC_RST[L]
AO_FSYNC AO_D[0] AO_SCLK AO_MCLK AO_IEC958
K_BUS_CLK K_BUS_REQ K_BUS_IN K_BUS_OUT
ATAPI Interface section (SHEET 15)
MADD1 to 22
64Mbit Flash
RD/WR[L] SYS_RESET[L] OE[L]/LDS[L] CS[0]
MADD1 to 4
MADD6 to 13
CS_3 SYS_RESET[L] EPG_INT[L]
UWE[L]/UDS[L] OE[L]/LDS[L]
EPG
IC1301
ALE MADD6 to 21
FLASH-ROM/EPG Section (SHEET 16)
F
TO CN4103
SHEET 8
TO CN4102
SHEET 8
TO CN4101
SHEET 8
TO DRIVE UNIT
TO HDD
IC1201
LH_AR6 to 21
IC1202
IC1203
G