Mitsubishi Electric GT14 User Manual page 418

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Series
Model
Q00JCPU
*1
Q00CPU
*1
Q01CPU
*1
Q02CPU
*1
Q02HCPU
*1
Q06HCPU
*1
Q12HCPU
*1
Q25HCPU
Q02PHCPU
Q06PHCPU
Q12PHCPU
Q25PHCPU
Q12PRHCPU
(Main base)
Q25PRHCPU
(Main base)
Q12PRHCPU
(Extension base)
Q25PRHCPU
(Extension base)
Q00UJCPU
MELSEC-Q
Q00UCPU
(Q mode)
Q01UCPU
Q02UCPU
Q03UDCPU
Q04UDHCPU
Q06UDHCPU
Q10UDHCPU
Q13UDHCPU
Q20UDHCPU
Q26UDHCPU
Q03UDECPU
Q04UDEHCPU
Q06UDEHCPU
Q10UDEHCPU
Q13UDEHCPU
Q20UDEHCPU
Q26UDEHCPU
Q50UDEHCPU
Q100UDEHCPU
Q03UDVCPU
Q04UDVCPU
Q06UDVCPU
Q13UDVCPU
Q26UDVCPU
Q12DCCPU-V
C Controller
Q24DHCCPU-V
module
Q24DHCCPU-LS
(Q Series)
Q26DHCCPU-LS
MELSEC-QS
QS001CPU
L02CPU
L06CPU
L26CPU
L26CPU-BT
L02CPU-P
MELSEC-L
L06CPU-P
L26CPU-P
L26CPU-PBT
L02SCPU
L02SCPU-P
Q02CPU-A
MELSEC-Q
Q02HCPU-A
(A mode)
Q06HCPU-A
22 - 2
22. COMPUTER LINK CONNECTION
22.1 Connectable Model List
Commu
Clock
nication
RS-232
RS-422
RS-232
RS-422
-
RS-232
RS-422
RS-232
RS-422
*3*4
*4
RS-232
RS-422
*4
-
RS-232
RS-422
RS-232
RS-422
Series
Refer to
MELSEC-QnA
(QnACPU)
22.2.2
22.2.2
MELSEC-QnA
(QnASCPU)
-
22.2.2
*1
*2
*3
*4
22.2.2
22.2.2
-
22.2.3
22.2.4
Commu
Model
Clock
nication
*2
Q2ACPU
*2
Q2ACPU-S1
RS-232
*2
Q3ACPU
RS-422
*2
Q4ACPU
*2
Q4ARCPU
*2
Q2ASCPU
*2
Q2ASCPU-S1
*2
Q2ASHCPU
*2
Q2ASHCPU-S1
A2UCPU
A2UCPU-S1
RS-232
A3UCPU
RS-422
A4UCPU
A2ACPU
A2ACPUP21
A2ACPUR21
A2ACPU-S1
A2ACPUP21-S1
(Continued to next page)
For the multiple CPU system configuration, use CPU
function version B or later.
If the A series computer link module is applied to the
QnACPU, the GOT can monitor the devices in the same
range on AnACPU.
However, the following devices cannot be monitored.
• Devices added to QnACPU
• Latch relays (L) and step relays (S)
(In case of QnACPU, the latch relay (L) and step relay (S)
are different from the internal relay (M). However,
whichever is specified, an access is made to the internal
relay.)
• File register (R)
Use only modules with the upper five digits of the serial No.
later than 12042.
Use the serial port of a serial communication module
controlled by another CPU on the multiple CPU.
Refer to
22.2.5
22.2.6

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