HP 54753A User Manual page 237

A slightly different situation can exist when the output of the MECL gate
switches from a logic 1 to a logic 0. The output of the MECL gate will turn off
if the termination resistor, R
impedance of the line. For the conditions in Figure 11-4, the output transistor
of the MECL gate will turn off at t = 0 for the negative going transition, when
> 70 Ω.
R
L
An equation for the value for R
as follows. The maximum voltage change at point A in Figure 11-4, (due to
turning off the output transistor) is the product of the dc current in the line and
the characteristic impedance of the line:
∆V
=
A
The voltage at point A is also dependent on the internal resistance of the driving
gate R and the internal logic swing.
o
∆V
A
Equating the two and solving for R
R =
L
Thus for the conditions given in Figure 11-4, the output transistor will turn off at
1.22 5
t = 0 when R = ------------------------------ - 5
L
The case for which the MECL output turns off is not in itself a serious problem,
although it makes a thorough analysis more difficult. Two reflection coefficients
must be used at the sending end and a piecewise approach used in determining
the voltage reflections.
Transmission Line Theory Applied to Digital Systems
, is somewhat larger than the characteristic
L
at which the gate will turn off can be derived
L
V'
( ) OH ( )
I Z = ----------------- - Z
LINE o o
R + Z
o o
Z
----------------- - ∆V ( )
o
=
INT
R + Z
o o
:
L
( )
V' R + Z
OH o o
----------------------------------- - R –
∆V
o
INT
( )
+ 50
– = 70Ω is exceeded.
0.9
Transmission Line Design
(6)
11-9