Philips 19HFL3007D/10 Service Manual page 41

8.6 Diagram 10-2-15 Tuner
Block diagram
RSSI
RF AGC
Differential
RF IF signal
Tuner
Tuner SDA
Tuner SCL
Pinning information
B15, MT5135AE (IC U1005)
MT5135AE
RSSI ADC
10-bit Integrated SAW
PGA
filter function
ADC
Micro-
SIF Master
controller
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
A15 97
A24 98
A12 99
A25 100
A7 101
VS2_ 102
A6 103
CMCIA_RESET 104
A5 105
WAIT_ 106
A4 107
A3 108
DVSS 109
DVDD33 110
REG_ 111
DVSS 112
DVDD10 113
A2 114
BVD2 115
A1 116
BVD1 117
A0 118
D8 119
D0 120
D9 121
D1 122
D10 123
D2 124
CD2_ 125
CI_INT 126 Host chip and TS interface
DVSS 127
DVDD33 128
1 2 3 4 5 6 7 8 9 10
Figure 8-8 Internal block diagram and pin configuration
IC Data Sheets
Other
demodulators
TS
interface
AGC
DVB-C
demodulator
DVB-T
demodulator
CI interface
MT5135AE
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
back to
div. table
TPM9.3HE LA
CAM
PCMCIA interface
PVR playback TS
PVR recording TS
CI+ controller
Demod TS
Demod TS
output
FEC decoder
SPI
transceiver
SPI interface
64 D5
63 D12
62 D4
61 D11
60 D3
59 CD1_
58 CHIP_CTRL
57 S2_TS_DATA7
56 S2_TS_DATA6
55 S2_TS_DATA5
54 S2_TS_DATA4
53 S2_TS_DATA3
52 S2_TS_DATA2
51 S2_TS_DATA1
50 DVDD33
49 DVSS
48 S2_TS_DATA0
47 S2_TS_VAL
46 S2_TS_SYNC
45 S2_TS_CLK
44 RF_AGC
43 IF_AGC
42 TUNER_CLK
41 TUNER_DATA
40 DVDD10
39 DVSS
38 AVDD33
37 AVDD12
36 IFPGA_INP
Analog interface 35 IFPGA_INN
34 AVSS12
33 EXT_CLKSEL
29 30 31 32
8. EN 41
Main
decoder
chip
19080_303_110317.eps
110330
2012-Sep-28