Functional Description; Baseband Description; Upp; Uemclite - Nokia RH-64 Service Manual

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RH-64
Nokia Customer Care
System module

Functional description

The BB core is based on UPP4M CPU. UPP4M takes care of all the signal processing and operation controlling
tasks of the mobile device. For power management, there is one main ASIC for controlling, charging and
supplying power UEMCLite plus a discrete power supply. The UEMCLite generates the main reset for the system.
Memories comprise 128 Mbit flash and 16 Mbit PsRAM. Memory devices are stacked on top of each other in a
single Combo package.
The UEMCLite also handles the interface to the RF and audio sections. This ASIC provides A/D and D/A conversion
of the in-phase and quadrate receive and transmit signal paths and also A/D and D/A conversions of received
and transmitted audio signals. Data transmission between UEMCLite and RF and the UPP4M is implemented
using different serial connections (CBUS, DBUS and RFBUS). UPP4M ASIC handles digital speech processing.
A real time clock function is integrated into UEMCLite, which utilizes the same 32 kHz-clock source as the sleep
clock. The SLCK/RTC runs all time when the phone battery is connected. It is running also when the phone is
switched off. In UEMCLite there is no back up battery/capacitor connection.
There are two audio transducers in the product; 13 mm speaker and a microphone. The speaker is used to
generate audios for earpiece, IHF and ringing tones. A separate audio amplifier drives the speaker. There is only
one microphone for both HS and IHF modes.
The display is a CSTN type color display with 65536 colors and 128 x 128 pixels with backlighting. The UI module
features a function key mat with a 4-way navigation key with a center selection key.

Baseband description

UPP

UPP (Universal Phone Processor) is the digital ASIC of the DCT4 generation base band. In LiteV2 BB the UPP4M_v3/
UPP4Mv4 and UPP2Mv2 are supported types. UPP4Mv3 includes 4.5 MBit internal RAM, ARM7TDMI rev4 16/32-
bit RISC MCU core, TI Lead3 16-bit DSP phase2+ core with DMA controller, ROM for MCU boot code and all digital
control logic. UPP general purpose IO (GENIO) can be used for predefined HW purpose or but they can also be
controlled with SW for product specific features.
Memory
This mobile uses two kinds of memories, Flash and Synchronous RAM (SRAM). These memories have are sharing
the same bus interface to UPP4M. SDRAM is used as the working memory. Interface is 16 bit wide data and 14
bit address. Memory clocking speed is 52 MHz. The SRAM size is 16 Mbits.
SRAM I/O is 1.8 V and core 1.8 V supplied by UEMCLite regulator VIO. All memory contents are lost if the supply
voltage is switched off.
Multiplexed flash memory interface is used to store the MCU program code and user data. The memory interface
is a burst type FLASH with multiplexed address/data bus, running at 52 MHz.
Configuration of flash memory is a 128 Mbit NOR flash memory. Flash I/O and core voltage are 1.8 V supplied
by UEMCLite's VIO.

UEMCLite

Power management in the RM-74/75 follows the DCT4 Core design, having anyhow less regulators than
traditional architecture. The UEMCLite, that is a low cost energy management ASIC with completely new design
contains for BB use two 2.78V LDO regulators, 1.8V linear regulator, programmable 1.0 - 1.5 V linear regulator
and 1.8/3.0 V LDO regulator. For RF use UEMCLite has five 2.78 V LDOs. In addition, the UEMCLite contains audio
codec, A/D converters, RF converters, many drivers, etc.
Below is a list of the supply voltages.
Page 8–6
Company Confidential
9243363 (Issue 1)
Copyright ©2005 Nokia. All Rights Reserved.

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