Mitsubishi Electric FX5 User Manual page 217

Melsec iq-f series
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Send & receive
A packet is sent once, and the status changes to the data receive wait status after the transmission completes normally. Then,
data is received from the counterpart device, and the process completes when the received data matches the receive packet
and the receiving process is performed. (Page 216 Operation Image and Data Structure of Predefined Protocol)
Settable receive packet (expected packet) is up to 16.
FX5 CPU module
Receive packet
(expected packet)
Data area (2)
Receiving
completed
The operation is as follows.
■Normal completion
FX5 CPU module
Drive S(P).CPRTCL
instruction
Completion device (d)
Completion status
indication device (d)+1
Counterpart device
■Error completion (transmission monitoring timeout error)
FX5 CPU module
Drive S(P).CPRTCL
instruction
Completion device (d)
Completion status
indication device (d)+1
Counterpart device
Terminator
Data area
Verification
mismatch
Header
Data area (1)
Verification
match
Header
Data area (2)
Send packet
Send packet
Send packet
Appendix 2 Operation Image and Data Structure of Predefined Protocol
Counterpart
device
Header
Receive wait time
Receive packe
Send packet
Receive packe
Receive wait time
Verification
mismatch
Receive packe
Verification match
Error occurred
Receive packe
APPENDIX
A
215

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