Aiwa CSD-A360LHL Service Manual page 30

IC DESCRIPTION-1/3 (LA9241ML)-2/2
Pin No. Pin Name
36 TES
37 HFL
38 SLOF
39, 40 CV–, CV+
41 RFSM
42 RFS-
43 SLC
44 SLI
45 DGND
46 FSC
47 TBC
48 NC
49 DEF
50 CLK
51 CL
52 DAT
53 CE
54 DRF
55 FSS
56 VCC2
57 REFI
58 VR
59 LF2
60 PH1
61 BH1
62 LDD
63 LDS
64 VCC1
I/O
O Pin from which TES signal is output to DSP.
"High Frequency Level" is used to judge whether the main beam position is on top of
O
bit or on top of mirror.
I Sled servo off control input pin.
I CLV error signal input pin from DSP.
O RF output pin.
RF gain setting and EFM signal 3T compensation constant setting pin together with
I
RFSM pin.
"Slice Level Control" is the output pin which controls the RF signal data slice level by
O
DSP.
I Input pin which control the data slice level by the DSP.
— Digital system GND.
O Output pin to which external focus search smoothing capacitor is connected.
I "Tracking Balance Control" EF balance variable range setting pin.
— Not connected.
O Disc defect detector output pin.
I Reference clock input pin. 4.23 MHz of the DSP is input.
I Microprocessor command clock input pin.
I Microprocessor command data input pin.
I Microprocessor command chip enable input pin.
O "Detect RF" RF level detector output.
"Focus Search Select" focus search mode (± search/+ search) select pin. (Not
I
connected)
— Servo system and digital system Vcc pin.
— Pin to which external bypass capacitor for reference voltage is connected.
O Reference voltage output pin.
I Disc defect detector time constant setting pin.
I Pin to which external capacitor for RF signal peak holding is connected.
I Pin to which external capacitor for RF signal bottom holding is connected.
O APC circuit output pin.
I APC circuit input pin.
— RF system Vcc pin.
Description
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