Figure 16-66 Mxp_Mr_2.5G And Mxpp_Mr_2.5G Faceplates; Block Diagram - Cisco ONS 15454 DWDM Installation And Operation Manual

16.8.6 MXP_MR_2.5G and MXPP_MR_2.5G Cards
Figure 16-66
MXP_MR_2.5G

16.8.6.2 Block Diagram

Figure 16-67
interfaces. Ports 1 and 2 can be used for GE, FC, or FICON. Ports 3 through 8 are for future use. There
are two SERDES blocks dedicated to the high-speed interfaces (GE, FC, and FICON) and two SERDES
blocks for future interfaces. A field programmable gate array (FPGA) is provided to support different
configurations for different modes of operation. This FPGA has a Universal Test and Operations
Physical Interface for ATM (UTOPIA) interface. A transceiver add-drop multiplexer (TADM) chip
Cisco ONS 15454 DWDM Installation and Operations Guide, R6.0
16-110
MXP_MR_2.5G and MXPP_MR_2.5G Faceplates
MXP
MR
2.5G
15xx.xx
15xx.xx
FAIL
ACT/STBY
SF
shows a block diagram of the MXP_MR_2.5G card. The card has eight SFP client
MXPP
MR
2.5G
15xx.xx
15xx.xx
FAIL
ACT/STBY
SF
MXPP_MR_2.5G
Chapter 16 Card Reference
April 2006