Design Features; Implementation Details - Abb Ac500-S Application Note

Safety programmable logic controllers
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Application Note for "Usage of AC500 digital standard I/Os in functional safety applications up to PL c (ISO 13849-1)", V1.0.0
3.4

Design features

3.4.1

Implementation details

The following steps shall be considered during the implementation of the proposed
approach (see Figure 5) for usage of digital standard I/Os in functional safety applica-
tions up to PL c (ISO 13849-1) in our example:
1. Use channel C16 of DC523 as an output in PM573 standard CPU program and
implement continuous pulsing (periodic TRUE and FALSE phases), as it is
specified in Figure 5, using e.g., TON FB. One can also define a dedicated cyclic
task on PM573 with 5 ms cycle and priority = 10 to continuously change the
value of channel C16 in the software loop keeping the periodic pulse behaviour
as it is shown in Figure 5.
NOTICE
2. Continuously read C0 input channel (with input delay parameter (refer to [4] for
details) set to 1 ms for input channels) of DC523 module in the application pro-
gram on PM573 CPU (make sure that the cycle time on the PM573 task is
properly selected, e.g., 2 ms cycle time with cyclic behaviour and priority = 11
for the task are proper ones for the given example).
3. Activate continuous sending of C0 channel value from PM573 application pro-
gram to SM560-S Safety CPU application program for safe test pattern super-
vision. To send C0 channel value to SM560-S from PM573, one can use:
a. SF_DPRAM_PM5XX_S_REC and SF_DPRAM_PM5XX_S_SEND FBs
from SafetyExt_AC500_V22.lib [1] or
b. Cyclic Non-safe Data Exchange [2], which has higher performance of
data
SF_DPRAM_PM5XX_S_SEND FBs.
We reserve all rights in this document. Reproduction, use or disclosure to third parties without express authority is strictly forbidden. Ó 2015 ABB Ltd.
The selected cycle time for test pulse generation task on standard
CPU program will influence the generated test pulse pattern.
The supervision of the test pattern (length of LOW and HIGH
phases) will be implemented on the Safety CPU. Thus, any devia-
tion of the test pulse pattern will be detected by the Safety CPU,
which will have to trigger the safe state for the given input channel
in case of a wrong test pattern.
transfer
than
using
SF_DPRAM_PM5XX_S_REC
and
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