Setting Of Dip Switch; Explanation Of Sw1 Bits; External View Of Dip Switch - Hitachi 902 Service Manual

(3)

Setting of DIP Switch

The DIP switch on the front panel is divided into operation mode setting part (SW1, 2, 3,
4) which determines operation at startup of the CPU board and program boot I/O setting
part (SW5, 6, 7, 8). This switch setting is reflected on the system status register on the
CPU board and can be read via software.
Switch No./Bit
SW1 SW2
D7 D6
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
Switch No./Bit
SW5 SW6
D3 D2

0

0

0

0

1

1

1

1

0

1

Explanation of SW1 Bits

SW3 SW4
D5 D4
0 0 Normal processing mode
0 1 Reserve
1 0 Reserve
1 1 Reserve
0 0 Continuous processing mode
(memory BRAM)
0 1 Continuous processing mode
(EEPROM)
1 0 Reserve
1 1 Reserve
0 0 Reserve
0 1 Reserve
1 0 Reserve
1 1 Reserve
0 0 T/M mode 1
0 1 T/M mode 2
1 0 T/M mode 3
1 1 T/M mode 4
SW7 SW8
D1 D0
0 0 SCSI device (H/D, etc.)
0 1 F/D
1 0 Reserve
1 1 Reserve
0 0 Reserve
0 1 I/O file ROM
1 0 EEPROM
1 1 Ethernet
 
Memory dump with boot I/O
 
Memory dump with any other
than boot I/O
Operation Mode
Boot I/O
10 - 5

External View of DIP Switch