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3.1.5 General Description
Figure3-1-2 details the block diagram of MT6223D. on a dual-processor architecture,
MT6223D integrates both an ARM7EJ-S core and 2 digital signal processor cores. ARM7EJ-S is
the main processor that is responsible for running 2G and 2.5G protocol software. Digital signal
processors handle the MODEM algorithms as well as advanced audio functions.
Except for some mixed-signal circuitries, the other building blocks in MT6223D are connected to
either the microcontroller or one of the digital signal processors.
Specifically, MT6223D consist of the following subsystems:
Microcontroller Unit (MCU) Subsystem - includes an ARM7EJ-S RISC processor and
its accompanying memory management and interrupt handling logics.
Digital Signal Processor (DSP) Subsystem - includes 2 DSP cores and their
accompanying memory, memory controller, and interrupt controller.
MCU/DSP Interface - where the MCU and the DSPs exchange hardware and
software information.
Microcontroller Peripherals - includes all user interface modules and RF control
interface modules.
Microcontroller Coprocessors - runs computing-intensive processes in place of
Microcontroller.
DSP Peripherals - hardware accelerators for GSM/GPRS/EGDE channel codec.
Voice Front End - the data path for converting analog speech from and to digital
speech.
Audio Front End - the data path for converting stereo audio from stereo audio source
Baseband Front End - the data path for converting digital signal from and to analog
signal of RF modules.
Timing Generator - generates the control signals related to the TDMA frame timing.
Power, Reset and Clock subsystem - manages the power, reset, and clock
distribution inside MT6223D
LDOs, Power-on sequences, swicthes and SIM level shifters.
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