Yamaha PSR-S710 Service Manual page 23

Hide thumbs Also See for PSR-S710:
Table of Contents

Advertisement

HD6417727F160CV (X2890B00) CPU
PIN
NAME
NO.
Vcc-RTC
1
2
XTAL2
EXTAL2
3
Vss-RTC
4
5
MD1
MD2
6
7
NMI
IRQ0/IRL0_/PTH[0]
8
IRQ1/IRL1_/PTH[1]
9
10
IRQ2/IRL2_/PTH[2]
IRQ3/IRL3_/PTH[3]
11
12
IRQ4/PTH[4]
VEPWC
13
VCPWC
14
15
MD5
/BREQ
16
17
/BACK
VssQ
18
CKIO2
19
20
VccQ
D31/PTB[7]
21
22
D30/PTB[6]
D29/PTB[5]
23
D28/PTB[4]
24
25
D27/PTB[3]
D26/PTB[2]
26
27
D25/PTB[1]
D24/PTB[0]
28
VssQ
29
30
D23/PTA[7]
VccQ
31
32
D22/PTA[6]
D21/PTA[5]
33
D20/PTA[4]
34
35
Vss
D19/PTA[3]
36
37
Vcc
D18/PTA[2]
38
D17/PTA[1]
39
40
D16/PTA[0]
D15
41
42
VssQ
D14
43
VccQ
44
45
D13
D12
46
47
D11
D10
48
D9
49
50
D8
D7
51
52
D6
VssQ
53
D5
54
55
VccQ
D4
56
57
D3
D2
58
D1
59
60
D0
A0
61
62
A1
A2
63
VssQ
64
65
A3
VccQ
66
67
A4
A5
68
A6
69
70
A7
A8
71
72
A9
A10
73
A11
74
75
VssQ
A12
76
77
VccQ
A13
78
A14
79
80
A15
A16
81
82
A17
A18
83
A19
84
85
A20
VssQ
86
87
A21
VccQ
88
A22
89
90
A23
Vss
91
92
A24
Vcc
93
A25
94
95
BS_/PTK[4]
RD_
96
97
WE0_/DQMLL
WE1_/DQMLU/WE
98
WE2_/DQMUL/ICIORD_/PTK[6]
99
100
VssQ
WE3_/DQMUU/ICIOWR_/PTK{7}
101
102
VccQ
RD/WR_
103
104
PTE[7]/PCC0RDY/AUDSYNC_
105
/CS0
/CS2
106
107
/CS3
/CS4/PTK[2]
108
109
/CS5/CE1A_/PTK[3}
110
/CS6/CE1B_
CE2A_/PTE[4]
111
112
CE2B_/PTE[5]
AFE_HC1/USB1d_DPLS/PTK[0]
113
114
AFE_RLYCNT_/USB1d_DMNS/PTK[1]
115
VssQ
AFE_SCLK/USB1d_TXDPLS
116
117
VccQ
PTM[7]/PTINT[7]/AFE_FS/USB1d_RCV
118
119
PTM[6]/PTINT[6]/AFE_RXIN/USB1d_SPEED
120
PTM[5]/PTINT[5]/AFE_TXOUT/USB1d_TXSE0
I/O
FUNCTION
-
Power supply for RTC (1.9V)
-
Not in use (XTAL for internal RTC)
-
-
Power supply for RTC (0V)
-
Clock mode setting
-
-
Not in use (Non-maskable interrupt request)
I
I
I
External interrupt request
I
I
O
VEE control pin for LCD panel
-
VCC control pin for LCD panel
-
Big endian setting
-
Not in use (bus request)
-
Bus acknowledge
-
VssQ
-
System clock output
-
VccQ
I/O
I/O
I/O
I/O
Data bus
I/O
I/O
I/O
I/O
-
VssQ
I/O
Data bus
-
VccQ
I/O
I/O
Data bus
I/O
-
Vss
I/O
Data bus
-
Vcc
I/O
I/O
Data bus
I/O
-
-
VssQ
-
Data bus
-
VccQ
-
-
-
-
Data bus
-
-
-
-
-
VssQ
-
Data bus
-
VccQ
-
-
-
Data bus
-
-
-
-
Address bus
-
-
VssQ
-
Address bus
-
VccQ
-
-
-
-
Address bus
-
-
-
-
-
VssQ
-
Address bus
-
VccQ
-
-
-
-
Address bus
-
-
-
-
-
VssQ
-
Address bus
-
VccQ
-
Address bus
-
-
Vss
-
Address bus
-
Vcc
-
Address bus
O
Not connected (bus cycle start signal)
-
Read strobe
O
Write 0 signal
O
Write 1 signal
O
Write 2 signal
-
VssQ
O
Write 3 signal
-
VccQ
O
Read/Write
O
I/O
-
Chip Select 0
-
Chip Select 2
-
Chip Select 3
O
Chip Select 4
O
Chip Select 5
O
Chip Select 6
O
Output port (SWP50 Reset)
O
Output port (PLG Board Reset)
O
SPD DATA
O
SPD CL
-
VssQ
I
Not in use (USB1 D+ transmission)
-
VccQ
I
I
Not in use
I
PIN
NAME
NO.
PTM[4]/PINT[4]/AFE_RDET_/USB1d_TXDMNS
121
Reserved/USB1d_SUSPEND
122
123
USB1_ovr_crnt/USBF_VBUS
USB2_ovr_crnt_
124
125
RTS2_/USB1d_TXENL
PTE[2]/USB1_pwr_en
126
PTE[1]/USB2_pwr_en
127
128
CKE/PTK[5]
/RAS3/PTJ[0]
129
130
Reserved/PTJ[1]
Reserved//CAS/PTJ[2]
131
VssQ
132
133
Reserved/PTJ[3]
VccQ
134
135
Reserved/PTJ[4]
Reserved/PTJ[5]
136
Vss
137
138
PTD[5]/CL1
Vcc
139
140
PTD[7]/DON
PTE[6]/M_DISP
141
PTE[3]/FLM
142
143
PTE[0]/TDO
PCC0RESET/DRACK0
144
145
PCC0DRV_/DACK0_
/WAIT
146
/RESETM
147
148
/ADTRG/PTH[5]
/IOIS16/PTG[7]
149
150
/ASEMD0
PTG[5]/ASEBRKAK_
151
PTG[4]
152
153
PCC0BVD2/PTG[3]/AUDATA[3]
PCC0BVD1/PTG[2]/AUDATA[2]
154
155
Vss
PCC0CD2/PTG[1]/AUDATA[1]
156
Vcc
157
158
PCC0CD1/PTG[0]/AUDATA[0]
VssQ
159
160
PTF[7]/PINT[15]/TRST_
VccQ
161
PTF[6]/PINT[14]/TMS
162
163
PTF[5]/PINT[13]/TDI
PTF[4]/PINT[12]/TCK
164
165
PTF[3]/PINT[11]/Reserved
PCCREG_/PTF[2]/Reserved
166
PCC0VS1_/PTF[1]/Reserved
167
168
PCC0VS2_/PTF[0]/Reserved
MD0
169
170
Vcc-PLL1
CAP1
171
Vss-PLL1
172
173
Vss-PLL2
CAP2
174
175
Vcc-PLL2
PCC0WAIT_/PTH[6]/AUDCK
176
Vss
177
178
Vcc
XTAL
179
180
EXTAL
LCD15/PTM[3]/PINT[10]
181
LCD14/PTM[2]/PINT[9]
182
183
LCD13/PTM[1]/PINT[8]
LCD12/PTM[0]
184
185
STATUS0/PTJ[6]
STATUS1/PTJ[7]
186
CL2/PTH[7]
187
188
VssQ
CKIO
189
190
VccQ
TxD0/SCPT[0]
191
SCK0/SCPT[1]
192
193
TxD_SIO/SCPT[2]
SIOMCLK/SCPT[3]
194
195
TxD2/SCPT[4]
SCK_SIO/SCPT[5]
196
SIOFSYNC/SCPT[6]
197
198
RxD0/SCPT[0]
RxD_SIO/SCPT[2]
199
200
Vss
RxD2/SCPT[4]
201
Vcc
202
203
SCPT[7]/CTS2_/IRQ5
LCD11/PTC[7]/PINT[3]
204
205
LCD10/PTC[6]/PINT[2]
LCD9/PTC[5]/PINT[1]
206
VssQ
207
208
LCD8/PTC[4]/PINT[0]
VccQ
209
210
LCD7/PTD[3]
LCD6/PTD[2]
211
LCD5/PTC[3]
212
213
LCD4/PTC[2]
LCD3/PTC[1]
214
215
LCD2/PTC[0]
LCD1/PTD[1]
216
LCD0/PTD[0]
217
218
DREQ0_/PTD[4]
LCK/UCLK/PTD[6]
219
220
/RESETP
CA
221
MD3
222
223
MD4
/Scan_testen
224
225
Avcc_USB
USB1_P
226
USB1_M
227
228
Avss_USB
USB2_P
229
230
USB2_M
Avcc_USB
231
Avss
232
233
AN[2]/PTL[2]
AN[3]/PTL[3]
234
235
AN[4]/PTL[4]
AN[5]/PTL[5]
236
Avcc
237
238
AN[6]/PTL[6]/DA[1]
AN[7]/PTL[7]/DA[0]
239
240
Avss
PSR-S710/PSR-S910
DML: IC3 (PSR-S710)
DMH: IC3 (PSR-S910)
I/O
FUNCTION
I
Not in use
O
I
USB function VBUS
-
USB2_HOST2 over current detection
O
Not in use
O
USB1 voltage control
O
USB2 voltage control
O
Enable (SDRAM)
O
RAS for SDRAM
O
Not in use
O
CAS for SDRAM
-
VssQ
O
Output port (DAC Reset)
-
VccQ
O
Output port (SIO Reset)
O
Output port (DAC Mute)
-
Vss
O
LCD line clock
-
Vcc
O
LCD DISPLAY ON
O
LCD alternater
O
LCD frame line marker
O
JTAG (test data output)
O
DMA request acceptance
O
DMA acknowledge
-
Hardware wait request
-
Manual reset request
I
Analog A/D trigger
I
-
Not in use
I
I
I
-
Vss
I
Not in use
-
Vcc
I
Not in use
-
VssQ
I
Not in use
-
VccQ
I
I
I
I
Not in use
I
I
I
-
Clock mode setting
-
Power supply for Vcc_PLL1 - PLL1(1.9V)
-
External capacitance for CAP1 _ PLL1
-
Power supply for Vss_PLL1 _ PLL1(0V)
-
Power supply for Vss_PLL2 _ PLL2 (0V)
-
External capacitance for CAP2 _ PLL2
-
Power supply for Vcc_PLL2 _ PLL2 (1.9V)
I
Not in use
-
Vss
-
Vcc
-
Clock oscillator
-
External clock
I
I
Not in use
I
I
Input port (Flash ROM RY/BY)
O
Output port (Flash ROM write protect)
O
Output port (Flash ROM ACC)
O
LCD clock output
-
VssQ
-
System clock input/output (for SDRAM)
-
VccQ
O
Output port for SCI
O
O
Not in use
O
O
Output port for SCI
O
Not in use
O
i
Receiving data 0
i
Not in use
-
Vss
i
Receiving data 2
-
Vcc
I
Not in use
O
Output port (PLG CLOCK ON/OFF)
O
Not in use
O
-
VssQ
O
Not in use
-
VccQ
O
LCD DATA7
O
LCD DATA6
O
LCD DATA5
O
LCD DATA4
O
LCD DATA3
O
LCD DATA2
O
LCD DATA1
O
LCD DATA0
I
DMA request
I
USB clock
-
Power on reset request
-
Hardware standby request
-
Bus width setting for area0
-
-
Test pin (fixed to 3.3V)
-
USB analog power supply (3.3V)
IO
USB1 data input/output (+)
IO
USB1 data input/output (-)
-
USB analog power supply (0V)
IO
USB2 data input/output (+)
IO
USB2 data input/output (-)
-
USB analog power supply (3.3V)
-
A/D analog power supply (0V)
I
I
AD converter input
I
I
-
A/D analog power supply (3.3V)
I
AD converter input
O
DA converter output (LCD contrast)
-
A/D analog power supply (0V)
23

Hide quick links:

Advertisement

Table of Contents
loading

This manual is also suitable for:

Psr-s910

Table of Contents