Schematic Diagram (Dsp) - Yamaha RX-V3300 Service Manual

A B

SCHEMATIC DIAGRAM (DSP)

1
4M DRAM
4.7
0.5
0.5
0.5
0.5
2
4.7
1.4
1.4
1.4
1.4
DIGITAL OUT INHIBIT
3.1
1.8
0 0 2 3.4
6
4.7
4.7 1 1.0
1.7
0
~
~
4.7
0 0 5 4.7
3
4 3.3
4.7
0
3.8
3
0
4.7
3.8
4.7
4.7
0 14
8 12 3.5
3 11
13
4.7 1
4.7 0.1
4.7
2 7
3.5 2.5
4 0
0
3.8
0
4.7
5
0 9
7 8 0
6
0 4.7
0 10
DUTY CORRECTOR
3.8
0
4.7
4
LEVEL CONVERT & SIGNAL DETECT
4.7 4.7
14
14
0 0 1
3.0 10 2 3
0
12 11 0 4.7
13
2.5 0
7
0 7
0
DIGITAL IN
3.0
2.5
0 0
4 13 11
4.7
1 2 3 0.4 0 12
0
5 9 8 5 9
0 0
6 4.7 0 6 4.7
5
DECODER
SRAM
Point 2 Pin 9 of IC504
0 0
0 0
0 0
0 3.4
0 0
6 3.4 0
0 0
0 0
0 0
0 0
3.4
3.4
0
0 0
0 0
0 0
0 0
3.4
0 0
0 0
0 0
2
0 0
7
IC526: XC9572XL-10TQ100C
CPLD
3
JTAG
JTAG Port
1
Controller
I/O
I/O
I/O
I/O
8
I/O
I/O
Blocks
I/O
I/O
I/O
3
I/O/GCK
1
I/O/GSR
2
I/O/GTS
9
C D E
Page 77 H5
to OPERATION (3)
REGULATOR
2.7 4.8
0 0.3 2.7 4.6 4.8
2.7
0
0
3.3 4.8
0.5
0.5
4.8
3.3
0.5
0.5
0
0
0
0.5
0.5
0.5
0.5
2.2
2.2
2.0
2.3
~
~
~
~
0
0
2.6
DSP/DOLBY/DTS
0
0
0
Point 1 Pin 1 of IC514
0
0
0
0.1
0
0
0
3.3
3.3
1.7
4.7
12
11 0.3
4.8 2.7
13 0
0.1
4.7
0.1 9
0
8
0.1
10 3.8
0
3.8
4
1
0 3.8
0
2.6
0
10
8
0
2.6
2.0
3.3
0 0
0
0 0
0
0
1.7
2.0
0 0
1.7
0
0 0
PLD
3.3
3.4
0
3.4
3.4 0
0
3.4
3.4
0
0
0 0
2.6
0
3.3
2.9 4.7
~ 0
3.1
3.1
3.1
0
In-System Programming Controller
IC524: CS5360-KSR
Stereo A/D Converter
54 Function
VA+ VD+ RSY MCLK OVFL FRAME SCLK LRCK
Block 1
18
3 6 18 7 2 10 8 12
Macrocells
1 to 18
9 SDATA
CMOUT 15 Voltage Reference Serial Output Interface 20 DIF0
19 DIF1
54
Function AINL- 16 + +
LP Filter +
Block 1 Digital Decimation High Pass
AINL+ 17 –
18 – – Filter Filter
S/H
Macrocells
1 to 18 Comparator
DAC
AINR- 14 + +
LP Filter +
Digital Decimation High Pass
AINR+ 13 –
– – Filter Filter
S/H
54 Function
Block 1 Comparator
DAC
18
Macrocells
1 to 18
4 5 11 1
AGND DGND PU HP DEFEAT
54
Function
Block 1
18
Macrocells
1 to 18
F G
Page 76 D1 Page 76
to FUNCTION to FUNCTION
BUFFER
MAIN L (ANALOG IN)
A/D CONVERTER
0
4.9
0
0
4.9
1.8
1.8
3.0
1.8
0.5 4.9
0.5
0.5
2.6
0
3.3
3.3
0
3.3
3.3
D/A CONVERTER
3.3
3.3 3.3 4.9
3.3 0
2.5
0.1
2.5
0.1 1.7
1.3 4.9
0.1
4.9
0.1 1.7
2.7
3.3 1.7
2.5
0.7 0
2.5
0.6 3.3
0 2.4
0
0
0 0
0 3.3 2.5
3.3 2.5
1.7
1.7 0
1.7
1.7
1.7
1.7
1.7
0
1.7
1.7
1.7
2.6
0
0
0
D/A CONVERTER
3.3
0
1.7
1.7
0.7
1.7
0
0.6
0
0
0.3
3.3
3.3
0
0
2.9
0
1.7
3.3
1.7
0
1.7
0
1.7
0
0
1.7
0
1.7
3.3
IC516: µPC29M33T-E1
IC517: PQ070XZ5MZP
Regulator Voltage Regulator
1 INPUT
Vin 1 3 Vo
Safety Drive
Limiter
Vc 2 4 Vadj
5 Amp.
GND
3 OUTPUT
Excessive Electric
Current Protection
2 GND
H I
E1
x: NOT USED
O: USED / APPLICABLE
4.9
4.9
4.9
0 2.5
4.9 11.4 11.8
0 2 2
8 8
2.5
2.5 2.5 2.5 2.5
3.4
1 3 1 3
2.5 2.5 2.5
2.5 2.5
2.5
2.5
2.5 2.5
5 5
2.5 7 7
2.5 2.5
6 6
2.5 2.5
0 0 4 4
2.5 2.5 2.5
-11.8
2.5 -11.8
0
0
MAIN L
11.4
2
8
1
2.5
3 2.4 11.4
1.4 2
2.5 8
1
5
2.5 7 1.4 3
0
6 47/50
2.5 2.4 0
0 -11.2
4
-11.8 0
0 -11.2
0
0
0
0
-11.2
11.4
2
8
2.5 1 5 0
3 2.4 1.4 7
6
2.5 0
4 47/50
5 1.4
2.5 7 -11.8
6
2.5 2.4
4
-11.8
CENTER
2 11.4
8
1
0
3
0
4 47/50
0 0 0
-11.8
-11.2
0
0
-11.2
0
0
0
0 6
7
5
0
0
2.5
2.5
2.5
2.5
11.4
8
4.9 6 7
1.8
2.9 2.8 5
0
0
1.8 0.6 0
3.4
2.5
0
2.5
2.9
0
0
2.5
2.5 0 0
0 -11.2
2.5
0
2.5
0 0 0
1.9 3 1
2
-11.3 0
1.9 4
-11.8
FRONT L
2.7K 11.4
4.3K 6
0 8 7
-11.3 0 5
0
0.1 0
-11.2 0
4.3K 2.7K
0 0
0
0
0
0 0 0
-11.2
4.3K 2.7K
0 3 0
1.8 1
0.1
-11.3 2
0
4
4.3K 2.7K 0
-11.8
LRCK1
REAR L
LRCK2
11.4
1.9
8 1
2
0 -11.3
0.1 3
0
47/50 0
1.9 -11.2
0
0
0
0 0
0
0
0 0
0
-11.2
0
0
1.9 0
0.1 47/50
7
0 5
-11.3 1.9 6 0
4
-11.8
IC515: MSM514260E-60JS
4Mbit DRAM
WE OE
13 27
Timing
RAS 14
Generator
I/O
Controller
LCAS 29
Output
UCAS 28 8 8
I/O
Buffers
Controller
DQ1~DQ8
Column
Input
9 Address 9 Column Decoders
8 8
Buffers Buffers
I/O
Internal Sense Amplifiers
Refresh 16 16
Selector
A0~A8 Address
Control Clock
Counter
Input
8
8
Buffers
Row
Row
9 9
Address Word Memory DQ9~DQ16
Deco-
Buffers Drivers Cells
ders
Output
8 8
Buffers
VCC
20
On Chip
VBB Generator
VSS 21
J K L
RX-V3300/DSP-AZ2
# All voltages are measured with a 10MΩ/V DC electric volt meter.
# Components having special characteristics are marked s and must be
replaced with parts having specifications equal to those originally
installed.
# Schematic diagram is subject to change without notice.
IC500: IS61LV6416-15K
64k x 16 High-speed CMOS Static RAM
A15 1 44 A0
A14 2 43 A1 64k X 16
A0 - A15 DECODER
A13 3 42 A2 MEMORY ARRAY
A12 4 41 /OE
A11 5 40 /UB
VCC
/CE 6 39 /LB
GND
I/O0 7 38 I/O15
I/O1 8 37 I/O14 I/O0 - I/O7
I/O
I/O2 9 36 I/O13 Lower Byte
DATA
I/O3 10 35 I/O12 COLUMN I/O
I/O8 - I/O15
CIRCUIT
Vcc 11 34 GND
Upper Byte
GND 12 33 Vcc
I/O4 13 32 I/O11
I/O5 14 31 I/O10
/CE
I/O6 15 30 I/O9
/OE
I/O7 16
29 I/O8
CONTROL
/WE
/WE 17 28 NC
CIRCUIT
A10 18 27 A3 /UB
A9 19 26 A4 /LB
A8 20 25 A5
A7 21 24 A6
NC 22 23 NC
IC501~502: TC74HCU04AF IC503: TC74HCT00AF
Hex Inverters Quad 2-Input Nand Gate
1A 1 14 Vcc
1A 1 14 VCC
1B 2 13 4B
1Y 2 13 6A
1Y 3 12 4A
2A 3 12 6Y
2A 4 11 4Y
2Y 4 11 5A 2B 5 10 3B
2Y 6 9 3A
3A 5 10 5Y
GND 7 8 3Y
3Y 6 9 4A
GND 7 8 4Y
IC505: TC74VHCT541AF IC507~509, 518~523: NJM2068MD
3-State Buffer IC513: NJM2904M
Dual OP-Amp.
/G1 1 20 Vcc
A1 2 19 /G2
OUT 1 1 8 +V CC
A2 3 18 Y1
–IN 1 2 7 OUT 2
A3 4 17 Y2
+ – + –
A4 5 16 Y3 +IN 3 6 –IN
1 2
A5 6 15 Y4
–V 4 5 +IN
CC 2
A6 7 14 Y5
A7 8 13 Y6
A8 9 12 Y7
GND 10 11 Y8
IC510 : CS4382-KQR
8-Channel D/A Converter
42 15 16 17 18 41 22
RST 19
Control Port (Stand-Alone Mode Select) External Mute Control
39 AOUTA1+
∆∑ DAC
Volume Control Interpolation Filter Analog Filter
40 AOUTA1-
VLS 43
Mixer
SCLK1 9
38 AOUTB1+
Volume Control Interpolation Filter ∆∑ DAC Analog Filter
7
37 AOUTB1-
SCLK2 12
35 AOUTA2+
10 ∆∑ DAC
Volume Control Interpolation Filter Analog Filter
36 AOUTA2-
SDIN1 8
Mixer
SDIN2 11
AOUTB2+
34
SDIN3 13 ∆∑ DAC
Volume Control Interpolation Filter Analog Filter
33 AOUTB2-
SDIN4
14
29 AOUTA3+
Volume Control Interpolation Filter ∆∑ DAC Analog Filter
AOUTA3-
30
Mixer
28 AOUTB3+
∆∑ DAC
Volume Control Interpolation Filter Analog Filter
27 AOUTB3-
25 AOUTA4+
Volume Control Interpolation Filter ∆∑ DAC Analog Filter
26 AOUTA4-
MCLK 6
Mixer
+2
24 AOUTB4+
∆∑ DAC
Volume Control Interpolation Filter Analog Filter
23 AOUTB4-
8
DSDxx 21 VQ
20 FILT+
4 5 31 32
IC511: PCM1730E-1/2K
D/A Converter
LRCK
4 IOUTL+
25
Current
Input
DATA 5 Segment
Interface
DAC IOUTL-
26
BCK
6
Advanced
VCOM2
20
Segment
Digital Bias IREF
21
RST 1 DAC
Filter &
19 VCOM1
MUTE 15 Vref
Modulator
22 VCOM3
FMT0
12 Function
Control
FMT1 13
Interface IOUTR-
16
FMT2 14 Current
Segment
DEMP0 10
DAC IOUTR+
17
DEMP1 11
System
Clock
System
SCKI Clock
7 ZERO Power
Manager Detect Supply
2 3 9 8 23 24 28 18 27
75