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Sharp SM-SX1 Service Manual page 42

1-bit amplifier
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SM-SX1/SX1W
IC803 VHiTDA1307/-1: 1-Bit Conversion (TDA1307) (2/2)
Pin No.
Port Name
39
CL
40
Vss
1
41
VDD3
42
RAB
Notes
1. These pins are configured as internal pull-down.
2. These pins are configured as internal pull-up.
ERROR CONCELMENT,
INTERPOLATION, MUTING
DSR 12
DSL 11
TEST1 36
TEST2 37
DA 38
CL 39
RAB 42
POR 20
V DD3 8
V DD1 21
V DDOSC 24
V DDAL 29
V DDAR 32
V DD2 41
27
DOL
Input/Output
Input (Note 2)
Clock input, to be generated by the microprocessor
Ground 1
Supply voltage 2
Input (Note 2)
Command/peak data request line
1fs AUDIO DATA INPUTS
EFAB
WS
SCK
SD
2
3
4
1
MULTIPLE FORMAT
INPUT INTERFACE
DIGITAL
OUTPUT
DIGITAL SILENCE DETECTION
DEEMPHASIS FILTER
FIR HALFBAND FILTER
STAGE 1: 1fs to 2fs
DC-CANCELING FILTER
PEAK DETECTION
FADE FUNCTION
VOLUME CONTROL
FIR HALFBAND FILTER
STAGE 2: 2 fs to 4 fs
FIR HALFBAND FILTER
STAGE 3: 4 fs to 8 fs
DITHER AND SCALING
3rd/4th ORDER
NOISE SHAPER
28
35
34
33
NDOL CDAC NDOR DOR
BITSTREAM DATA OUTPUTS
Figure 42 BLOCK DIAGRAM OF IC
TDA1307
19 RESYNC
10 DOBM
13 DSTB
5 SBCL
6 SBDA
25 V SSOSC
22 XTAL1
CRYSTAL
OSCIL-
23 XTAL2
LATOR
15 CMIC
7 CDEC
14 CLC1
17 CLC2
18 CDCC
9 V SS2
16 V SS3
30 V SSAL
31 V SSAR
40 V SS1
26
MODE
– 42 –
Function
WS
1
SCK
2
SD
3
EFAB
4
SBCL
5
SBDA
6
CDEC
7
V DDC3
8
V SSC2
9
DOBM
10
TDA1307
DSL
11
DSR
12
DSTB
13
CLC1
14
CMIC
15
V SSC3
16
CLC2
17
CDCC
18
RESYNC
19
POR
20
V DDC1
21
42
RAB
V DDC2
41
V SSC1
40
CL
39
DA
38
TEST2
37
TEST1
36
CDAC
35
NDOR
34
DOR
33
V DDAR
32
V SSAR
31
V SSAL
30
V DDAL
29
NDOL
28
DOL
27
MODE
26
V SSOSC
25
V DDOSC
24
23
XTAL2
XTAL1
22

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