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Sharp SM-SX1 Service Manual page 41

1-bit amplifier
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IC803 VHiTDA1307/-1: 1-Bit Conversion (TDA1307) (1/2)
• Outline
The TDA1307 is an advanced oversampling digital filter employing bitstream conversion technology, which has been designed
for use in premium performance digital audio applications. Audio data is input to the TDA1307 through its multiple-format interface.
Any of the four formats (IIS, Sony 16, 18 or 20-bit) are acceptable. By using a highly accurate audio data processing structure,
including 8 times oversampling digital filtering and up to 4th order noise shaping, a high quality bitstream is produced which, when
used in the recommended combination with the TDA1547 bitstream DAC, provides the optimum in dynamic range and signal-to-
noise performance. With the TDA1307, a high degree of versatility is achieved by a multitude of functional features and their easy
accessibility; error concealment functions, audio peak data information and an advanced patented digital fade function are
accessible through a simple microprocessor command interface, which also provides access to various integrated system settings
and functions.
Pin No.
Port Name
1
WS
2
SCK
3
SD
4
EFAB
5
SBCL
6
SBDA
7*
CDEC
8
VDD3
9
VSS2
10*
DOBM
11*
DSL
12*
DSR
13
DSTB
14
CLC1
15*
CMIC
16
VSS3
17
CLC2
18
CDCC
19*
RESYNC
20
POR
21
VDD1
22
XTAL1
23
XTAL2
24
VDDOSC
25
VSSOSC
26*
MODE
27
DOL
28*
NDOL
29
VDDAL
30
VSSAL
31
VSSAR
32
VDDAR
33
DOR
34*
NDOR
35
CDAC
36, 37
TEST1, TEST2
38
DA
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Input/Output
Input
Word select input to data interface
Input
Clock input to data interface
Input
Data input to interface
Input (Note 1)
Error flag: (active HIGH) input from decoder chip indicating unreliable data
Input
Subcode clock: a 10-bit burst clock (typ. 2.8224 MHz) input which synchronizes the subcode data
Input
Subcode data: a 10-bit burst of data, including flags and sync bits, serially input once per
frame, clocked by burst clock input SBCL
Output
Decoder clock output: frequency division programmable by means of pins 14 (CLC1) and 17
(CLC2) to output 192, 256, 384 or 768 times fs
Positive supply 3
Ground 2
Output
Digital audio output: this output contains digital audio samples which have received
interpolation, attenuation and muting plus subcode data. Transmission is in biphase-mark
code.
Output
Digital silence detected (active LOW) on left channel
Output
Digital silence detected (active LOW) on right channel
Input (Note 2)
DOBM stand-by mode enforce pin (active HIGH)
Input
Application mode programming pin for CDEC (pin 7) frequency division
Output
Clock output, provided to be used as running clock by microprocessor (in master mode only),
output 96fs
Ground 3
Input
Application mode programming pin for CDEC (pin 7) frequency division
Input
Master/Slave mode selection pin
Output
Resynchronization: out-of-lock indication from data input section (active HIGH)
Input (Note 2)
Power-on reset (active LOW)
Supply voltage 1
Input
Crystal oscillator terminal: local crystal oscillator sense
Output
Crystal oscillator output: drive output to crystal or forced input in slave mode
Positive supply connection to crystal oscillator circuitry
Ground connection to crystal oscillator circuitry
Input (Note 2)
Evaluation mode programming pin (active LOW); in normal operation, this pin should be left
open-circuit or connected to the positive supply
Output
Data output left channel to bitstream DAC TDA1547
Output
Complementary data output left channel to TDA1547
Positive supply connection to output data driving circuitry, left channel
Ground connection to output data driving circuitry, left channel
Ground connection to output data driving circuitry, right channel
Positive supply connection to output data driving circuitry, right channel
Output
Data output right channel to TDA1547
Output
Complementary data output right channel to TDA1547
Output
Clock output to bitstream DAC TDA1547
Input (Note 1)
Test mode input. In normal operation this pin should be connected to ground
Input/Output
Bidirectional data line intended for control data from the microprocessor and peak data from
(Note 2)
the TDA1307
Function
– 41 –
SM-SX1/SX1W

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