Sony HCD-DZ777K Service Manual page 69

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Pin No.
Pin Name
53
LIMITSW
54
MSW
55
DVDD18
56 to 62
HA2 to HA8
63, 64
HA18, HA19
65
DVDD3
66
XWR
67 to 74
HA16 to HA9
75
HA20
76
XROMCS
77
HA1
78
XRD
79, 80
HD0, HD1
81
DVSS
82 to 86
HD2 to HD6
87
HA21
88
RESERVED
89
HD7
90
DVSS
91, 92
HA17, HA0
93
DVDD18
94
FWR
95
REV
96
DVDD3
97
IFSDO
98
IFCK
99
xIFCS
100
IFSDI
101
SCL
102
SDA
103
CKSW
104
OCSW
105
RXD
106
TXD
107
ICE
108
xSYSRST
109
RESERVED
110
xIFBSY
111
DQM0
112
EEWP
113 to 117
RD7 to 3
118
DVDD3
119 to 121
RD2 to RD0
122 to 129
RD15 to RD8
130
TSD_M
131
DVDD3
132
DQM1
133
_RWE
134
_CAS
135
_RAS
136
_RCS
137, 138
BA0, BA1
139
RA10
140, 141
RA0, RA1
142
DVDD18
143, 144
RA2, RA3
HCD-DZ265K/DZ266K/DZ270K/DZ570K/DZ777K
I/O
I
LIMIT SW signal input
O
DVD/CD PD –VR select signal output
Power supply (+1.8V)
O
Flash ROM address bus A2 to A8 output
O
Flash ROM address bus A18, A19 output
Power supply (+3.3V)
O
Flash ROM write signal output
O
Flash ROM address bus A16 to A9 output
Flash ROM address bus A20 output
O
Flash ROM chip select signal output
O
Flash ROM address bus A1 output
O
Flash ROM read signal output
I/O
Flash ROM data bus D0, D1 input/output
Ground terminal
I/O
Flash ROM data bus D2 to D6 input/output
I/O
Flash ROM data bus D21 input/output
Not used (Open)
I/O
Flash ROM data bus D7 input/output
Ground terminal
O
Flash ROM address bus A17, A0 output
O
Flash ROM data bus D18 input/output
O
Loading motor control (FWR) signal output
O
Loading motor control (REV) signal output
Power supply (+3.3V)
O
CPU I/F serial data output
O
CPU I/F serial clock output
O
CPU I/F chip select output
I
CPU I/F serial data input
O
EEPROM serial clock output
I/O
EEPROM serial data input/output
I
Chuck/Tray detect switch signal input
I
Chuck/Tray detect switch signal input
I
RXD signal input from Jig
O
TXD signal output to Jig
O
Not used (Open)
I
System reset signal input
I
Not used (Open)
I
Busy signal input from CPU I/F
O
SDRAM lower byte mask signal output
I
EEPROM ready/Busy wake up signal input
I/O
SDROM data bus D7 to D3 input/output
Power supply (+3.3V)
I/O
SDROM data bus D2 to D0 input/output
I/O
SDROM data bus D15 to D8 input/output
I
TSD signal input
Power supply (+3.3V)
O
SDRAM lower byte mask signal output
O
SDRAM write enable signal output
O
SDRAM column address strobe signal output
O
SDRAM row address strobe signal output
O
SDRAM chip select signal output
O
SDRAM bank address 0, 1 output
O
SDRAM address bus A10 output
O
SDRAM address bus A0, A1 output
Power supply (+1.8V)
O
SDRAM address bus A0, A3 output
Description
69

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